On 25/01/2018 13:57, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-01-25 13:33:32)- if (engine && ((caps & engine->caps) != caps)) - return -EINVAL; + do { + engine = i915->engine[_VCS(instance)]; + instance ^= 1; + vcs_instances--; + } while ((caps & engine->caps) != caps && vcs_instances > 0); + + if ((caps & engine->caps) != caps) + return -EINVAL; + + timeline = i915_gem_context_lookup_timeline_class(eb->ctx, + VIDEO_DECODE_CLASS); + spin_lock_irq(&timeline->lock); + prev_req = list_first_entry_or_null(&timeline->requests, + struct drm_i915_gem_request, + ctx_link); + spin_unlock_irq(&timeline->lock);This isn't doing anything yet as we aren't using the timeline. The idea is sound though, we need to rejig timelines to make them more flexible so that we can combine them to use one per-queue. Ok.
I think it works - as far as I looked at the trace.pl HTML output it seems to.
The purpose is to simulate single stream of execution, so this is a new timeline I added which is per ctx and per engine class. Submissions set up an await on a previous request on the virtual engine, so when the balancer decides to move between instances it ensures they do not run in parallel.
In a real implementation this either wouldn't be needed or would live at some other, more natural, level.
Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
