Op 04-09-17 om 17:58 schreef Ville Syrjälä: > On Mon, Sep 04, 2017 at 12:39:25PM +0200, Maarten Lankhorst wrote: >> Op 31-08-17 om 20:48 schreef Ville Syrjälä: >>> On Wed, Aug 30, 2017 at 09:57:03PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: >>>> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >>>> >>>> Make the min_pixclk thing less confusing by changing it to track >>>> the minimum acceptable cdclk frequency instead. This means moving >>>> the application of the guardbands to a slightly higher level from >>>> the low level platform specific calc_cdclk() functions. >>>> >>>> The immediate benefit is elimination of the confusing 2x factors >>>> on GLK/CNL+ in the audio workarounds (which stems from the fact >>>> that the pipes produce two pixels per clock). >>>> >>>> v2: Keep cdclk higher on CNL to workaround missing DDI clock voltage handling >>>> v3: Squash with the CNL cdclk limits patch (DK) >>>> v4: s/intel_min_cdclk/intel_pixel_rate_to_cdclk/ (DK) >>>> >>>> Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> >>>> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> >>>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> >>>> Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> >>>> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> >>>> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >>> I didn't get any objections from the CNL camp, so I went ahead and >>> pushed the series. Thanks for the reviews. >>> >> I seem to have a WARN_ON during init now on my broadwell, likely related to this series? >> >> [ 13.105310] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem >> [ 13.132264] systemd-journald[159]: Successfully sent stream file descriptor to service manager. >> [ 13.161016] WARN_ON(min_cdclk < 0) > Hmm. I think I need to see the full dmesg to figure this one out. > [ 188.354997] [drm:intel_modeset_init [i915]] 3 display pipes available. [ 188.356575] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 188.357067] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 540000 kHz [ 188.357220] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 540000 kHz ... <snip some hw radout spam> [ 188.363648] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:640x480] for CRTC state ffff8800c79e2200 [ 188.363784] [drm:intel_crtc_compute_min_cdclk [i915]] required cdclk (607500 kHz) exceeds max (540000 kHz) [ 188.363848] WARN_ON(min_cdclk < 0) ... [ 188.368005] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][setup_hw_state] [ 188.368155] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 188.368276] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 [ 188.368390] [drm:intel_dump_pipe_config [i915]] requested mode: [ 188.368692] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 1286 540000 640 656 752 800 480 490 492 525 0x40 0xa [ 188.368833] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 188.368897] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 1286 540000 640 656 752 800 480 490 492 525 0x40 0xa [ 188.369041] [drm:intel_dump_pipe_config [i915]] crtc timings: 540000 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa [ 188.369235] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 720x400, pixel rate 607500 [ 188.369366] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x028001e0, enabled [ 188.369490] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 188.369600] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 188.369719] [drm:intel_dump_pipe_config [i915]] planes on this crtc Is this enough info? _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
