On 5/26/23 11:05, Marek Vasut wrote:
On 5/15/23 18:02, Philippe CORNU wrote:
Hi,
The genmask of regsiter SSCR, BPCR & others were setted accordly to
the chipset stm32f4.
So that means:
F4 -> 2048x2048 framebuffer
H7/MP1 -> 4096x4096 framebuffer
?
Worse
F4 is 2048x2048
F7 is 4096x2048
MP1 is 4096x4096
and there is no IDR register on F4/F7 like on MP1, or is there ?
How else can we tell those LTDC versions apart ?
Dear Marek,
Many thanks for your patch (and sorry for this late reply).
Your patch is good and fixes this ltdc driver source code vs. the
related reference manual.
imho, it will not be an issue for F4 & F7 series if these bit-fields
are "bigger" as I am pretty sure stm32 MCUs are not really using such
high resolutions.
Yannick already replied with his reviewed-by. I add my
Acked-by: Philippe Cornu <philippe.cornu@xxxxxxxxxxx>
If you agree, I will merge your patch really soon.
I would say there is no rush, so let's get this done right .
Dear Yannick,
You may add to your todo list to double check if there is a need to
detect stm32 MCUs vs. these bit-field sizes...
Can we use a compatible string , or I think there is some ID register ?
[...]
btw I only received this email now, odd, I wonder whether it was stuck
in some SMTP server. Sorry for the delayed reply, it was out of my control.
Hi Marek,
Thank you for your feedback, I agree it is better to fix this properly.
Note: After a quick check, I'm 99% sure that the smtp problem was on my
end (although I don't understand why I know we've had some issues with
the mailing lists over the past few weeks), so all my apologies for that :-)
Hi Yannick,
May I ask you please to prepare this clean up (taking into account all
ltdc versions).
Many thanks
Philippe :-)
