On 10/14/22 15:42, Yannick FERTRE wrote:
Hi Marek,
Hello Yannick,
The genmask of regsiter SSCR, BPCR & others were setted accordly to the
chipset stm32f4.
So that means:
F4 -> 2048x2048 framebuffer
H7/MP1 -> 4096x4096 framebuffer
?
We should then also update STM_MAX_FB_WIDTH/STM_MAX_FB_HEIGHT per SoC type ?
You can see more details on page 493 of reference manual RM0090:
https://www.st.com/resource/en/reference_manual/DM00031020-.pdf
With future hardware, all of these registers will aligned on 16bits.
I would like to know if you use a display which resolution exceed 2048.
Not at all, 480x640 .
The display is just flaky and I'm trying to figure out what's wrong with
it, so I'm checking all over the place and noticed this discrepancy.
