On 10/14/22 17:55, Marek Vasut wrote:
On 10/14/22 15:42, Yannick FERTRE wrote:Hi Marek,Hello Yannick,The genmask of regsiter SSCR, BPCR & others were setted accordly to the chipset stm32f4.So that means: F4 -> 2048x2048 framebuffer H7/MP1 -> 4096x4096 framebuffer ?
Worse F4 is 2048x2048 F7 is 4096x2048 MP1 is 4096x4096 and there is no IDR register on F4/F7 like on MP1, or is there ? How else can we tell those LTDC versions apart ?
