Hi Kedar, > -----Original Message----- > From: Appana Durga Kedareswara Rao [mailto:appanad@xxxxxxxxxx] > Sent: 2017年12月21日 22:00 > To: Wen He <wen.he_1@xxxxxxx>; Vinod Koul <vinod.koul@xxxxxxxxx> > Cc: Leo Li <leoyang.li@xxxxxxx>; dmaengine@xxxxxxxxxxxxxxx; Jiafei Pan > <jiafei.pan@xxxxxxx>; Jiaheng Fan <jiaheng.fan@xxxxxxx> > Subject: RE: [PATCH 1/4] dma: fsl-qdma: add qDMA Command queue mode > driver > > Hi, > > Thanks for the patch.. . > <Snip> > >> > > Ah that would be duplicate. How about making it common and > >> > > abstracting this as FSL_DMA_IN/OUT and using in both drivers? > >> > > >> > OK, but for now we are on rush to let this merged. Could we apply > >> > current version fist, then I will discuss with author of that macro > >> > to get it > >> done? Thank you. > >> > >> Am really sorry but that is not how upstreaming works. We dont do > >> this and we certainly don't rush. > >> > > > >Okay, got it. through discuss with author, I know the fsldma.c is early > >freescale powerpc Socs driver and DMA_IN/OUT used. > >So I want will and below defined FSL_DMA_IN/OUT instead DMA_IN/OUT in > >fsldma.h and using in both drivers. > >Is that ok? > > > >#ifdef CONFIG_PPC > >static void ioread32(const u32 __iomem *addr) { > > return in_le32(addr); > >} > > > >static void iowrite32(u32 __iomem *addr, u32 val) { > > out_le32(addr, val); > >} > > > >static void ioread32be(const u32 __iomem *addr) { > > return in_be32(addr); > >} > > > >static void iowrite32be(u32 __iomem *addr, u32 val) { > > out_be32(addr, val); > >} > >#endif > > > >#define FSL_DMA_IN(fsl_dma, addr, width) > \ > > (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ? > \ > > ioread##width##be(addr) : > ioread##width(addr)) > > > >#define FSL_DMA_OUT(fsl_dma, addr, val, width) > \ > > (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ? > \ > > iowrite##width##be(val, addr) : > >iowrite##width(val, addr)) > > > > Not sure whether it is useful or not. > To differentiate b/w big-endian and little endian you can read a register and > based on that You can differentiate sub sequent writes/reads in the driver. > > For your reference > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir > .free-electrons.com%2Flinux%2Flatest%2Fsource%2Fdrivers%2Fnet%2Fcan% > 2Fxilinx_can.c%23L1156&data=02%7C01%7Cwen.he_1%40nxp.com%7Ca251 > 456a259248ad0d3408d5487b2257%7C686ea1d3bc2b4c6fa92cd99c5c30163 > 5%7C0%7C0%7C636494616067137548&sdata=v8%2B%2BOJPvMhM3rM21% > 2FgaYIM%2Fxp8XlEnMweQhev2iRbrk%3D&reserved=0 > This endian mode is not CPU endian mode, is IP(qdma) Module endian mode. For now NXP QorIQ Layerscape Processors including 13 socs, same IP on different soc has may be different endian-mode. fsl_qdma->feature = of_property_read_bool(np, "big-endian"); In above, IP endian-mode defined in dts file, fsl_qdma_probe() need read dts node be used for getting IP endian mode. So, Maybe I can't follow your reference. For your reference https://elixir.free-electrons.com/linux/latest/source/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi Regards, Wen > Regards, > Kedar. > > >Best Regards, > >Wen > > > >> -- > >> ~Vinod > >> -- > >> To unsubscribe from this list: send the line "unsubscribe dmaengine" > >> in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo > >> info at > >https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fvger > . > >> > kernel.org%2Fmajordomo-info.html&data=02%7C01%7Cwen.he_1%40nxp.co > >> > m%7C74567b527be2494f807008d547c47ce9%7C686ea1d3bc2b4c6fa92cd99 > >> > c5c301635%7C0%7C0%7C636493831608931495&sdata=0nw8F8Vpcszm5WS > >> ixNlv2PsonEJu1ippSVwyARvwzLM%3D&reserved=0 > >韬{.n?壏煯壄?%娝lzwm呴b濍Р骒r笡y贇zx"濊Ф洝塄}财爖?j:+v > 墾?珣赙 > >zZ+€?zf＂穐殘啳嗃iz?畐ア?櫒璀??撷f ��.n��������+%������w��{.n��������)�)�� jg��� �����ݢj����G���� ���j:+v���w�m������w�������h�����٥
