On Wed, Mar 12, 2025 at 03:06:32PM +0000, Gupta, Suraj wrote: > [AMD Official Use Only - AMD Internal Distribution Only] > > > -----Original Message----- > > From: Andrew Lunn <andrew@xxxxxxx> > > Sent: Wednesday, March 12, 2025 8:29 PM > > To: Gupta, Suraj <Suraj.Gupta2@xxxxxxx> > > Cc: Russell King <linux@xxxxxxxxxxxxxxx>; Pandey, Radhey Shyam > > <radhey.shyam.pandey@xxxxxxx>; andrew+netdev@xxxxxxx; > > davem@xxxxxxxxxxxxx; edumazet@xxxxxxxxxx; kuba@xxxxxxxxxx; > > pabeni@xxxxxxxxxx; robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx; > > Simek, Michal <michal.simek@xxxxxxx>; netdev@xxxxxxxxxxxxxxx; > > devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm- > > kernel@xxxxxxxxxxxxxxxxxxx; git (AMD-Xilinx) <git@xxxxxxx>; Katakam, Harini > > <harini.katakam@xxxxxxx> > > Subject: Re: [PATCH net-next V2 2/2] net: axienet: Add support for 2500base-X only > > configuration. > > > > Caution: This message originated from an External Source. Use proper caution > > when opening attachments, clicking links, or responding. > > > > > > > > On Wed, Mar 12, 2025 at 02:25:27PM +0100, Andrew Lunn wrote: > > > > > > + /* AXI 1G/2.5G ethernet IP has following synthesis options: > > > > > > + * 1) SGMII/1000base-X only. > > > > > > + * 2) 2500base-X only. > > > > > > + * 3) Dynamically switching between (1) and (2), and is not > > > > > > + * implemented in driver. > > > > > > + */ > > > > > - Keeping previous discussion short, identification of (3) depends on > > > how user implements switching logic in FPGA (external GT or RTL > > > logic). AXI 1G/2.5G IP provides only static speed selections and there > > > is no standard register to communicate that to software. > > > > So if anybody has synthesised it as 3) this change will break their system? > > > > Andrew > > It will just restrict their system to (2) Where as before, it was doing SGMII/1000base-X only. So such systems break? Andrew
