AXI 1G/2.5G ethernet IP has following synthesis options:
1) SGMII/1000base-X only.
2) 2500base-X only.
3) dynamically switching between (1) and (2).
Add support for 2500base-X only configuration.
Co-developed-by: Harini Katakam <harini.katakam@xxxxxxx>
Signed-off-by: Harini Katakam <harini.katakam@xxxxxxx>
Signed-off-by: Suraj Gupta <suraj.gupta2@xxxxxxx>
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 2 +-
.../net/ethernet/xilinx/xilinx_axienet_main.c | 24 +++++++++++++++----
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index 5ff742103beb..ded3e32999d5 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -274,7 +274,7 @@
#define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
-#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
+#define XAE_EMMC_LINKSPD_1000_2500 0x80000000 /* Link Speed mask for 1000 or 2500 Mbit */
/* Bit masks for Axi Ethernet PHYC register */
#define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 054abf283ab3..0885ce201b0a 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -2583,6 +2583,7 @@ static struct phylink_pcs *axienet_mac_select_pcs(struct phylink_config *config,
struct axienet_local *lp = netdev_priv(ndev);
if (interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX ||
interface == PHY_INTERFACE_MODE_SGMII)
return &lp->pcs;
@@ -2616,8 +2617,9 @@ static void axienet_mac_link_up(struct phylink_config *config,
emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
switch (speed) {
+ case SPEED_2500:
case SPEED_1000:
- emmc_reg |= XAE_EMMC_LINKSPD_1000;
+ emmc_reg |= XAE_EMMC_LINKSPD_1000_2500;
break;
case SPEED_100:
emmc_reg |= XAE_EMMC_LINKSPD_100;
@@ -2627,7 +2629,7 @@ static void axienet_mac_link_up(struct phylink_config *config,
break;
default:
dev_err(&ndev->dev,
- "Speed other than 10, 100 or 1Gbps is not supported\n");
+ "Speed other than 10, 100, 1Gbps or 2.5Gbps is not supported\n");
break;
}
@@ -3055,7 +3057,8 @@ static int axienet_probe(struct platform_device *pdev)
"error registering MDIO bus: %d\n", ret);
if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII ||
- lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
+ lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
+ lp->phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
np = of_parse_phandle(pdev->dev.of_node, "pcs-handle", 0);
if (!np) {
/* Deprecated: Always use "pcs-handle" for pcs_phy.
@@ -3083,8 +3086,19 @@ static int axienet_probe(struct platform_device *pdev)
lp->phylink_config.dev = &ndev->dev;
lp->phylink_config.type = PHYLINK_NETDEV;
lp->phylink_config.mac_managed_pm = true;
- lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
- MAC_10FD | MAC_100FD | MAC_1000FD;
+ lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
+
+ /* AXI 1G/2.5G ethernet IP has following synthesis options:
+ * 1) SGMII/1000base-X only.
+ * 2) 2500base-X only.
+ * 3) Dynamically switching between (1) and (2), and is not
+ * implemented in driver.
+ */
+
+ if (axienet_ior(lp, XAE_ABILITY_OFFSET) & XAE_ABILITY_2_5G)
+ lp->phylink_config.mac_capabilities |= MAC_2500FD;
+ else
+ lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
__set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces);
if (lp->switch_x_sgmii) {
--
2.25.1
