> > On Wed, Mar 12, 2025 at 02:25:27PM +0100, Andrew Lunn wrote: > > > > + /* AXI 1G/2.5G ethernet IP has following synthesis options: > > > > + * 1) SGMII/1000base-X only. > > > > + * 2) 2500base-X only. > > > > + * 3) Dynamically switching between (1) and (2), and is not > > > > + * implemented in driver. > > > > + */ > - Keeping previous discussion short, identification of (3) depends > on how user implements switching logic in FPGA (external GT or RTL > logic). AXI 1G/2.5G IP provides only static speed selections and > there is no standard register to communicate that to software. So if anybody has synthesised it as 3) this change will break their system? Andrew
