Add PM8775 ADC5 GEN3 Channel info and bindings for the MBG Temp alarm peripheral found on PM8775 pmic. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@xxxxxxxxxxx> --- .../bindings/thermal/qcom-spmi-mbg-tm.yaml | 86 ++++++++++++++++++++++ .../iio/adc/qcom,spmi-adc5-gen3-pm8775.h | 41 +++++++++++ 2 files changed, 127 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..909373eb758e4a8b7c2bbd0022c56ab2e823ca13 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-spmi-mbg-tm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SPMI PMIC MBG Thermal Monitoring + +maintainers: + - Satya Priya Kakitapalli <quic_skakitap@xxxxxxxxxxx> + +description: + Qualcomm's MBG(Master Bandgap) temperature alarm monitors the die + temperature and generates an interrupt if the PMIC die temperature is + over a set of programmable temperature thresholds. It allows monitoring + for both hot and cold, LVL1 and LVL2 thresholds, which makes it different + from the existing temp alarm peripheral. The interrupt comes over SPMI + and the MBG's fault status register gives details to understand whether + it is a hot/cold and LVL1/LVL2 violation. + +allOf: + - $ref: thermal-sensor.yaml# + +properties: + compatible: + const: qcom,spmi-pm8775-mbg-tm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + io-channels: + items: + - description: ADC channel, which reports chip die temperature. + + io-channel-names: + const: thermal + + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - io-channels + - io-channel-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h> + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + pmm8654au_0_tz: temperature-sensor@d700 { + compatible = "qcom,spmi-pm8775-mbg-tm"; + reg = <0xd700>; + interrupts = <0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8775_1_adc PM8775_ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + }; + + thermal-zones { + pm8775-mbg0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8654au_0_tz>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + }; +... diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h new file mode 100644 index 0000000000000000000000000000000000000000..33f5454367777b10fda248476a0abd17da86ecf6 --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H + +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> + +#define PM8775_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PM8775_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PM8775_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) +#define PM8775_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8775_ADC5_GEN3_AMUX1_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM) +#define PM8775_ADC5_GEN3_AMUX2_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM) +#define PM8775_ADC5_GEN3_AMUX3_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM) +#define PM8775_ADC5_GEN3_AMUX4_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM) +#define PM8775_ADC5_GEN3_AMUX5_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM) +#define PM8775_ADC5_GEN3_AMUX6_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM) +#define PM8775_ADC5_GEN3_AMUX1_GPIO9(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO) +#define PM8775_ADC5_GEN3_AMUX2_GPIO10(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO) +#define PM8775_ADC5_GEN3_AMUX3_GPIO11(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO) +#define PM8775_ADC5_GEN3_AMUX4_GPIO12(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO) + +/* 100k pull-up2 */ +#define PM8775_ADC5_GEN3_AMUX1_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX2_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX3_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX4_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX5_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX6_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX1_GPIO9_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) +#define PM8775_ADC5_GEN3_AMUX2_GPIO10_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) +#define PM8775_ADC5_GEN3_AMUX3_GPIO11_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) +#define PM8775_ADC5_GEN3_AMUX4_GPIO12_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) + +#define PM8775_ADC5_GEN3_VPH_PWR(sid) ((sid) << 8 | ADC5_GEN3_VPH_PWR) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H */ -- 2.25.1
