Hi, Geert,
On 10.10.2024 18:22, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Fri, Aug 30, 2024 at 3:02 PM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>>
>> Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>> ---
>>
>> Changes in v3:
>> - added CPG clock, power domain, reset
>> - and assigned-clocks, assigned-clock-parents to configure the
>> VBATTCLK
>> - included dt-bindings/clock/r9a08g045-vbattb.h
>
> Thanks for your patch!
>
>> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
>> @@ -160,6 +161,22 @@ i2c3: i2c@10090c00 {
>> status = "disabled";
>> };
>>
>> + rtc: rtc@1004ec00 {
>
> Please insert this after serial@1004b800, to preserve sort order.
You're right. I though I have already checked this.
>
>> + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
>> + reg = <0 0x1004ec00 0 0x400>;
>> + interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "alarm", "period", "carry";
>> + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>;
>> + clock-names = "bus", "counter";
>> + assigned-clocks = <&vbattb VBATTB_MUX>;
>> + assigned-clock-parents = <&vbattb VBATTB_XC>;
>
> Don't the assigned-clock* properties belong in the board DTS?
It makes sense to be in the board DTS, indeed.
> In addition, I think they should be documented in the DT bindings,
> and be made required, so board developers don't forget about them.
It would be better, indeed.
Thank you,
Claudiu Beznea
>
>> + power-domains = <&cpg>;
>> + resets = <&cpg R9A08G045_VBAT_BRESETN>;
>> + status = "disabled";
>> + };
>> +
>> vbattb: vbattb@1005c000 {
>> compatible = "renesas,r9a08g045-vbattb";
>> reg = <0 0x1005c000 0 0x1000>;
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
> Geert
>
