Hi Peng,
thanks for your patch.
Am Sonntag, 28. April 2024, 14:22:20 CEST schrieb Peng Fan (OSS):
> From: Peng Fan <peng.fan@xxxxxxx>
>
> i.MX95 features 6 A55 Cores, ARM Mali GPU, ISP, ML acceleration NPU,
> and Edgelock secure enclave security. This patch is to add a minimal
> dtsi, with cpu cores, coresight, scmi, gic, uart, mu, sdhc, lpi2c added.
>
> Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx95-clock.h | 187 +++++
> arch/arm64/boot/dts/freescale/imx95-power.h | 55 ++
> arch/arm64/boot/dts/freescale/imx95.dtsi | 1152 +++++++++++++++++++++++++++
> 3 files changed, 1394 insertions(+)
>
> [snip]
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> new file mode 100644
> index 000000000000..f52023ec7f0c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> [snip]
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + aips2: bus@42000000 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + reg = <0x0 0x42000000 0x0 0x800000>;
> + ranges = <0x42000000 0x0 0x42000000 0x8000000>,
> + <0x28000000 0x0 0x28000000 0x10000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + mu7: mailbox@42430000 {
> + compatible = "fsl,imx95-mu";
> + reg = <0x42430000 0x10000>;
> + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> + mu8: mailbox@42730000 {
Please sort all nodes by address.
> + compatible = "fsl,imx95-mu";
> + reg = <0x42730000 0x10000>;
> + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> + wdog3: watchdog@42490000 {
> + compatible = "fsl,imx93-wdt";
> + reg = <0x42490000 0x10000>;
> + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> + timeout-sec = <40>;
> + fsl,ext-reset-output;
Isn't this board specific?
> + status = "disabled";
> + };
> +
> + tpm3: pwm@424e0000 {
> + compatible = "fsl,imx7ulp-pwm";
> + reg = <0x424e0000 0x1000>;
> + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> [snip]
> + };
> +
> + aips3: bus@42800000 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + reg = <0 0x42800000 0 0x800000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x42800000 0x0 0x42800000 0x800000>;
> +
> + usdhc1: mmc@42850000 {
> + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
> + reg = <0x42850000 0x10000>;
> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
> + <&scmi_clk IMX95_CLK_WAKEUPAXI>,
> + <&scmi_clk IMX95_CLK_USDHC1>;
> + clock-names = "ipg", "ahb", "per";
> + assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>;
> + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
> + assigned-clock-rates = <400000000>;
> + bus-width = <8>;
> + fsl,tuning-start-tap = <1>;
> + fsl,tuning-step= <2>;
Isn't this board specific? Or is there a hardware limitation?
> + status = "disabled";
> + };
> +
> + usdhc2: mmc@42860000 {
> + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
> + reg = <0x42860000 0x10000>;
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
> + <&scmi_clk IMX95_CLK_WAKEUPAXI>,
> + <&scmi_clk IMX95_CLK_USDHC2>;
> + clock-names = "ipg", "ahb", "per";
> + assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>;
> + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
> + assigned-clock-rates = <200000000>;
Why is usdhc2 only 200 MHz but usdhc1 400 MHz?
> + bus-width = <4>;
> + fsl,tuning-start-tap = <1>;
> + fsl,tuning-step= <2>;
Isn't this board specific? Or is there a hardware limitation?
> + status = "disabled";
> + };
> +
> + usdhc3: mmc@428b0000 {
> + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
> + reg = <0x428b0000 0x10000>;
> + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
> + <&scmi_clk IMX95_CLK_WAKEUPAXI>,
> + <&scmi_clk IMX95_CLK_USDHC3>;
> + clock-names = "ipg", "ahb", "per";
No need to configure IMX95_CLK_USDHC3?
> + bus-width = <4>;
> + fsl,tuning-start-tap = <1>;
> + fsl,tuning-step= <2>;
> + status = "disabled";
> + };
> + };
> +
> + gpio2: gpio@43810000 {
> + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
> + reg = <0x0 0x43810000 0x0 0x1000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
> + <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> + clock-names = "gpio", "port";
> + };
> +
> + gpio3: gpio@43820000 {
> + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
> + reg = <0x0 0x43820000 0x0 0x1000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
> + <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> + clock-names = "gpio", "port";
> + };
> +
> + gpio4: gpio@43840000 {
> + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
> + reg = <0x0 0x43840000 0x0 0x1000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
> + <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> + clock-names = "gpio", "port";
> + };
> +
> + gpio5: gpio@43850000 {
> + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
> + reg = <0x0 0x43850000 0x0 0x1000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
> + <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> + clock-names = "gpio", "port";
> + };
> +
> + aips1: bus@44000000 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + reg = <0x0 0x44000000 0x0 0x800000>;
> + ranges = <0x44000000 0x0 0x44000000 0x800000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + mu1: mailbox@44220000 {
> + compatible = "fsl,imx95-mu";
> + reg = <0x44220000 0x10000>;
> + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_BUSAON>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> + mu2: mailbox@445b0000 {
> + compatible = "fsl,imx95-mu";
> + reg = <0x445b0000 0x1000>;
> + ranges;
> + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #mbox-cells = <2>;
> +
> + sram0: sram@445b1000 {
> + compatible = "mmio-sram";
> + reg = <0x445b1000 0x400>;
> + ranges = <0x0 0x445b1000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + scmi_buf0: scmi-sram-section@0 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x0 0x80>;
> + };
> +
> + scmi_buf1: scmi-sram-section@80 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x80 0x80>;
> + };
> + };
I guess this MU depends on the system manager firmware, no?
> + };
> +
> + mu3: mailbox@445d0000 {
> + compatible = "fsl,imx95-mu";
> + reg = <0x445d0000 0x10000>;
> + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_BUSAON>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> + mu4: mailbox@445f0000 {
> + compatible = "fsl,imx95-mu";
> + reg = <0x445f0000 0x10000>;
> + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_BUSAON>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> + mu6: mailbox@44630000 {
> + compatible = "fsl,imx95-mu";
> + reg = <0x44630000 0x10000>;
> + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_BUSAON>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> + tpm1: pwm@44310000 {
> + compatible = "fsl,imx7ulp-pwm";
> + reg = <0x44310000 0x1000>;
> + clocks = <&scmi_clk IMX95_CLK_BUSAON>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + tpm2: pwm@44320000 {
> + compatible = "fsl,imx7ulp-pwm";
> + reg = <0x44320000 0x1000>;
> + clocks = <&scmi_clk IMX95_CLK_TPM2>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + lpi2c1: i2c@44340000 {
> + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x44340000 0x10000>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_LPI2C1>,
> + <&scmi_clk IMX95_CLK_BUSAON>;
> + clock-names = "per", "ipg";
> + status = "disabled";
> + };
> +
> + lpi2c2: i2c@44350000 {
> + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x44350000 0x10000>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_LPI2C2>,
> + <&scmi_clk IMX95_CLK_BUSAON>;
> + clock-names = "per", "ipg";
> + status = "disabled";
> + };
> +
> + lpspi1: spi@44360000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
> + reg = <0x44360000 0x10000>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_LPSPI1>,
> + <&scmi_clk IMX95_CLK_BUSAON>;
> + clock-names = "per", "ipg";
> + status = "disabled";
> + };
> +
> + lpspi2: spi@44370000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
> + reg = <0x44370000 0x10000>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_LPSPI2>,
> + <&scmi_clk IMX95_CLK_BUSAON>;
> + clock-names = "per", "ipg";
> + status = "disabled";
> + };
> +
> + lpuart1: serial@44380000 {
> + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
> + "fsl,imx7ulp-lpuart";
> + reg = <0x44380000 0x1000>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_LPUART1>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + lpuart2: serial@44390000 {
> + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
> + "fsl,imx7ulp-lpuart";
> + reg = <0x44390000 0x1000>;
> + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_LPUART2>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + adc1: adc@44530000 {
> + compatible = "nxp,imx93-adc";
> + reg = <0x44530000 0x10000>;
> + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk IMX95_CLK_ADC>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
Please sort the nodes by address.
> + };
> +
> + aips4: bus@49000000 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + reg = <0x0 0x49000000 0x0 0x800000>;
> + ranges = <0x49000000 0x0 0x49000000 0x800000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + smmu: iommu@490d0000 {
> + compatible = "arm,smmu-v3";
> + reg = <0x490d0000 0x100000>;
> + interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> + #iommu-cells = <1>;
> + status = "disabled";
> + };
> + };
> +
> + gpio1: gpio@47400000 {
> + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
> + reg = <0x0 0x47400000 0x0 0x1000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + clocks = <&scmi_clk IMX95_CLK_M33>,
> + <&scmi_clk IMX95_CLK_M33>;
> + clock-names = "gpio", "port";
> + status = "disabled";
I'm wondering of there should be a comment here that gpio1 usually is under
exclusive control of SM.
> + };
> +
> + elemu0: mailbox@47520000 {
> + compatible = "fsl,imx95-mu-ele";
> + reg = <0x0 0x47520000 0x0 0x10000>;
> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> + elemu1: mailbox@47530000 {
> + compatible = "fsl,imx95-mu-ele";
> + reg = <0x0 0x47530000 0x0 0x10000>;
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> + elemu2: mailbox@47540000 {
> + compatible = "fsl,imx95-mu-ele";
> + reg = <0x0 0x47540000 0x0 0x10000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> + elemu3: mailbox@47550000 {
> + compatible = "fsl,imx95-mu-ele";
> + reg = <0x0 0x47550000 0x0 0x10000>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
> + };
> +
> + elemu4: mailbox@47560000 {
> + compatible = "fsl,imx95-mu-ele";
> + reg = <0x0 0x47560000 0x0 0x10000>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> + elemu5: mailbox@47570000 {
> + compatible = "fsl,imx95-mu-ele";
> + reg = <0x0 0x47570000 0x0 0x10000>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> + v2x_mu: mailbox@47350000 {
> + compatible = "fsl,imx95-mu-v2x";
> + reg = <0x0 0x47350000 0x0 0x10000>;
> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
> + };
> +
> + v2x_mu6: mailbox@47320000 {
> + compatible = "fsl,imx95-mu-v2x";
> + reg = <0x0 0x47320000 0x0 0x10000>;
> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
> + };
Please sort nodes by address.
Best regards,
Alexander
> + };
> +};
>
>
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