On 14/04/2024 22:21, Arınç ÜNAL wrote:
> On 14.04.2024 22:12, Krzysztof Kozlowski wrote:
>> On 14/04/2024 18:59, Arınç ÜNAL wrote:
>>>>> + };
>>>>> +
>>>>> + memory@0 {
>>>>> + device_type = "memory";
>>>>> + reg = <0x00000000 0x08000000>,
>>>>> + <0x88000000 0x08000000>;
>>>>> + };
>>>>> +
>>>>> + nvram@1c080000 {
>>>>> + compatible = "brcm,nvram";
>>>>> + reg = <0x1c080000 0x00180000>;
>>>>
>>>> Why is this outside of soc? Both soc node and soc DTSI?
>>>
>>> I don't maintain the SoC device tree files so I don't know. The nvram node
>>> doesn't exist on any of the device tree files included by this device tree.
>>
>> There are two problems here:
>> 1. This looks like SoC component and such should not be in board DTS.
>> Regardless whether you maintain something or not, you should not add
>> incorrect code. Unless this is correct code, but then please share some
>> details.
>
> NVRAM is described as both flash device partition and memory mapped NVMEM.
> This platform stores NVRAM on flash but makes it also memory accessible.
>
> As device partitions are described in board DTS, the nvram node must also
Sorry, but we do not talk about partitions. Partitions are indeed board
property. But the piece of hardware, so NVMEM, is provided by SoC.
> be defined there as its address and size will be different by board. It has
> been widely described on at least bcm4709 and bcm47094 SoC board DTS files
> here.
These not proper arguments. What you are saying here is that SoC does no
have nvram at address 0x1c08000. Instead you are saying there some sort
of bus going out of SoC to the board and on the board physically there
is some NVRAM sort of memory attached to this bus.
>
>>
>> 2. You cannot have MMIO node outside of soc. That's a W=1 warning.
>
> I was not able to spot a warning related to this with the command below.
> The source code directory is checked out on a recent soc/soc.git for-next
> tree. Please let me know the correct command to do this.
>
> $ make W=1 dtbs
> [...]
> DTC arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dtb
> arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0.dtsi:10.18-19.5: Warning (avoid_unnecessary_addr_size): /nand-controller@18028000/nand@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
> also defined at arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch8.dtsi:13.9-17.3
> also defined at arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts:137.9-160.3
> arch/arm/boot/dts/broadcom/bcm-ns.dtsi:24.28-47.4: Warning (unique_unit_address_if_enabled): /chipcommon-a-bus@18000000: duplicate unit-address (also used in node /axi@18000000)
> arch/arm/boot/dts/broadcom/bcm-ns.dtsi:323.22-328.4: Warning (unique_unit_address_if_enabled): /mdio@18003000: duplicate unit-address (also used in node /mdio-mux@18003000)
Hm, indeed, that way it works. Actually should work if we allow soc@0
and memory@x, obviously.
Anyway, it is outside of soc node and soc dtsi, which leads to previous
point - you claim that it is not physically in the SoC package. How is
it connected? If it is on the board, why does it have brcm compatible,
not some "ti,whatever-eeprom-nvram"?
Best regards,
Krzysztof
