On 06/11/2023 09:55, Xianwei Zhao wrote: > The patchset adds support for the peripheral and PLL clock controller > found on the Amlogic C3 SoC family, such as C302X or C308L. > > Changes since V5 [3]: > - Fix some typo and modify formart for MARCO. Suggested by Jerome. > - Add pad clock for peripheral input clock in bindings. > - Add some description for explaining why ddr_dpll_pt_clk and cts_msr_clk are out of tree. > Changes since V4 [10]: > - Change some fw_name of clocks. Suggested by Jerome. > - Delete minItem of clocks. > - Add CLk_GET_RATE_NOCACHE flags for gp1_pll > - Fix some format. and fix width as 8 for mclk_pll_dco. > - exchange gate and divder for fclk_50m clock. > - add CLK_SET_RATE_PARENT for axi_a_divder & axi_b_divder. > - add CLK_IS_CRITICAL for axi_clk > - Optimized macro define for pwm clk. > - add cts_oscin_clk mux between 24M and 32k > - add some missing gate clock, such as ddr_pll. Where are all these versions? Please provide links. Best regards, Krzysztof
