On Tue, 4 Jul 2023 at 08:49, Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> wrote: > > Add PLL clock inputs from PLL clock generator. > > Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx> > --- > .../bindings/clock/starfive,jh7110-syscrg.yaml | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > index 84373ae31644..5ba0a885aa80 100644 > --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > @@ -27,6 +27,9 @@ properties: > - description: External I2S RX left/right channel clock > - description: External TDM clock > - description: External audio master clock > + - description: PLL0 > + - description: PLL1 > + - description: PLL2 > > - items: > - description: Main Oscillator (24 MHz) > @@ -38,6 +41,9 @@ properties: > - description: External I2S RX left/right channel clock > - description: External TDM clock > - description: External audio master clock > + - description: PLL0 > + - description: PLL1 > + - description: PLL2 > > clock-names: > oneOf: > @@ -52,6 +58,9 @@ properties: > - const: i2srx_lrck_ext > - const: tdm_ext > - const: mclk_ext > + - const: pll0_out > + - const: pll1_out > + - const: pll2_out > > - items: > - const: osc > @@ -63,6 +72,9 @@ properties: > - const: i2srx_lrck_ext > - const: tdm_ext > - const: mclk_ext > + - const: pll0_out > + - const: pll1_out > + - const: pll2_out > > '#clock-cells': > const: 1 > @@ -93,12 +105,14 @@ examples: > <&gmac1_rgmii_rxin>, > <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, > <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, > - <&tdm_ext>, <&mclk_ext>; > + <&tdm_ext>, <&mclk_ext>, > + <&pllclk 0>, <&pllclk 1>, <&pllclk 2>; > clock-names = "osc", "gmac1_rmii_refin", > "gmac1_rgmii_rxin", > "i2stx_bclk_ext", "i2stx_lrck_ext", > "i2srx_bclk_ext", "i2srx_lrck_ext", > - "tdm_ext", "mclk_ext"; > + "tdm_ext", "mclk_ext", > + "pll0_out", "pll1_out", "pll2_out"; > #clock-cells = <1>; > #reset-cells = <1>; > }; > -- > 2.25.1 >
