On 2023/7/5 6:23, Conor Dooley wrote: > On Tue, Jul 04, 2023 at 02:46:06PM +0800, Xingyu Wu wrote: >> Add PLL clock inputs from PLL clock generator. >> >> Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> > > As expected this produces warnings for the existing, in-tree, > devicetrees which go away when the later dts patches are applied. > It'd be good to mention that its intentional if you end up sending > another version of the series. > > Otherwise, this looks good to me too. > > Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > Thanks, I will add the mentions in next version. Best regards, Xingyu Wu
