On 12/07/2023 13:09, Eric Lin wrote: > On Sat, Jul 01, 2023 at 10:22:25AM +0200, Krzysztof Kozlowski wrote: >> On 28/06/2023 18:31, Eric Lin wrote: >> >>>>>> >>>>>>> + - enum: >>>>>>> + - sifive,pL2Cache0 >>>>>>> + - sifive,pL2Cache1 >>>>>> >>>>>> What is "0" and "1" here? What do these compatibles represent? Why they >>>>>> do not have any SoC related part? >>>>> >>>>> The pL2Cache1 has minor changes in hardware, but it can use the same >>>>> pl2 cache driver. >>>> >>>> Then why aren't they compatible? >>>> >>> >>> The pL2Cache1 has removed some unused bits in the register compared to >>> pl2Cache0. >>> From the hardware perspective, they are not compatible but they can >>> share the same pl2 cache driver in software. >> >> So they are compatible... If they were not compatible, you wouldn't be >> able to use the same match in the driver. >> >>> Thus, we would like to keep both. It would be great if you can provide >>> some suggestions. Thanks. >> >> I propose to make them compatible, like every other piece of SoC. I >> don't see any benefit of having them separate. >> > > Hi Krzysztof, > > Sorry for the late reply. > The pl2 cache is our internal platform IP and is not part of any SoC. > > The reason why this driver is compatible with the hardware "pl2cache0" and hardware "pl2cache1" > is that it doesn't program the different parts of the config register > However, our internal software (e.g., bare-metal software) will program these different parts, > so it needs to rely on the different compatible string to identify the hardware. > > Additionally, we would like the compatible strings to reflect which hardware is being used Thanks. I don't understand how does it contradicts anything I said. So you do agree with me? Or what? Best regards, Krzysztof
