Hi Chris, chris.packham@xxxxxxxxxxxxxxxxxxx wrote on Mon, 3 Jul 2023 15:50:42 +1200: > Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to > mode 3 so a specific compatible value is needed. > > Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx> > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> I need DT-binding maintainer's ack to take this patch, but this commit did not receive feedback (positive of negative) from them and is no longer in their patchwork. Can you please resend the series? The other patches LGTM. > --- > > Notes: > Changes in v3: > - Collect ack from Conor > Changes in v2: > - Keep compatibles in alphabetical order > - Explain AC5 limitations in commit message > > .../devicetree/bindings/mtd/marvell,nand-controller.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml > index a10729bb1840..1ecea848e8b9 100644 > --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml > +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml > @@ -16,6 +16,7 @@ properties: > - const: marvell,armada-8k-nand-controller > - const: marvell,armada370-nand-controller > - enum: > + - marvell,ac5-nand-controller > - marvell,armada370-nand-controller > - marvell,pxa3xx-nand-controller > - description: legacy bindings Thanks, Miquèl
