Hi Conor, Thanks for your comment. > -----Original Message----- > From: Conor Dooley <conor@xxxxxxxxxx> > Sent: 2023年7月5日 0:54 > To: G.N. Zhou (OSS) <guoniu.zhou@xxxxxxxxxxx> > Cc: linux-media@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; dl-linux-imx > <linux-imx@xxxxxxx>; mchehab@xxxxxxxxxx; > laurent.pinchart@xxxxxxxxxxxxxxxx; robh+dt@xxxxxxxxxx; > krzysztof.kozlowski+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx; > jacopo.mondi@xxxxxxxxxxxxxxxx > Subject: Re: [PATCH 1/2] media: dt-bindings: Add binding doc for i.MX93 MIPI > CSI-2 > > Hey, > > I know little about media bindings, so only got a single comment for you. > > On Mon, Jul 03, 2023 at 07:37:33PM +0800, guoniu.zhou@xxxxxxxxxxx wrote: > > From: "Guoniu.zhou" <guoniu.zhou@xxxxxxx> > > > > Add new binding documentation for DesignWare Core MIPI CSI-2 receiver > > and DPHY found on NXP i.MX93. > > > > Signed-off-by: Guoniu.zhou <guoniu.zhou@xxxxxxx> > > --- > > .../bindings/media/nxp,dwc-mipi-csi2.yaml | 140 > ++++++++++++++++++ > > 1 file changed, 140 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml > > b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml > > new file mode 100644 > > index 000000000000..ece6fb8991d4 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml > > The filename of the binding should match the compatible. > > > @@ -0,0 +1,140 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/nxp,dwc-mipi-csi2.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: NXP i.MX93 MIPI CSI-2 Host Controller receiver > > + > > +maintainers: > > + - G.N. Zhou <guoniu.zhou@xxxxxxx> > > + > > +description: |- > > + The MIPI CSI-2 receiver found on i.MX93 originates from Synopsys > > + DesignWare Core and it implements the CSI-2 protocol on the host > > + side and a DPHY configured as a Slave acts as the physical layer. > > + Two data lanes are supported on i.MX93 family devices and the data > > + rate of each lane support up to 1.5Gbps. > > + > > + While the CSI-2 receiver is separate from the MIPI D-PHY IP core, > > + the PHY is completely wrapped by the CSI-2 controller and expose a > > + control interface which only can communicate with CSI-2 controller > > + This binding thus covers both IP cores. > > + > > +properties: > > + compatible: > > + enum: > > + - fsl,imx93-mipi-csi2 > > Everywhere else you say NXP, why use Freescale here? Due to history reason, all i.MX platforms of NXP use "fsl" as vendor abbreviation prefix. > > Cheers, > Conor.
