On Wed, Jul 05, 2023 at 01:30:38AM +0000, G.N. Zhou (OSS) wrote: > > > diff --git > > > a/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml > > > b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml > > > new file mode 100644 > > > index 000000000000..ece6fb8991d4 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/media/nxp,dwc-mipi-csi2.yaml > > > > The filename of the binding should match the compatible. > > > > > @@ -0,0 +1,140 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/media/nxp,dwc-mipi-csi2.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: NXP i.MX93 MIPI CSI-2 Host Controller receiver > > > + > > > +maintainers: > > > + - G.N. Zhou <guoniu.zhou@xxxxxxx> > > > + > > > +description: |- > > > + The MIPI CSI-2 receiver found on i.MX93 originates from Synopsys > > > + DesignWare Core and it implements the CSI-2 protocol on the host > > > + side and a DPHY configured as a Slave acts as the physical layer. > > > + Two data lanes are supported on i.MX93 family devices and the data > > > + rate of each lane support up to 1.5Gbps. > > > + > > > + While the CSI-2 receiver is separate from the MIPI D-PHY IP core, > > > + the PHY is completely wrapped by the CSI-2 controller and expose a > > > + control interface which only can communicate with CSI-2 controller > > > + This binding thus covers both IP cores. > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - fsl,imx93-mipi-csi2 > > > > Everywhere else you say NXP, why use Freescale here? > > Due to history reason, all i.MX platforms of NXP use "fsl" as vendor abbreviation prefix. Okay. Please update the filename to patch the "fsl" compatible then. Cheers, Conor.
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