Add support for the lpass audio clock controller found on SC8280XP based
devices. This would allow lpass peripheral loader drivers to control the
clocks and bring the subsystems out of reset.
Currently this patch only supports resets as the Q6DSP is in control of
LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg
channel.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
---
drivers/clk/qcom/lpasscc-sc8280xp.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/clk/qcom/lpasscc-sc8280xp.c b/drivers/clk/qcom/lpasscc-sc8280xp.c
index 118320f8ee40..e221ae2d40ae 100644
--- a/drivers/clk/qcom/lpasscc-sc8280xp.c
+++ b/drivers/clk/qcom/lpasscc-sc8280xp.c
@@ -13,6 +13,26 @@
#include "common.h"
#include "reset.h"
+static const struct qcom_reset_map lpass_audio_csr_sc8280xp_resets[] = {
+ [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
+ [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
+ [LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 },
+};
+
+static struct regmap_config lpass_audio_csr_sc8280xp_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .name = "lpass-audio-csr",
+ .max_register = 0x1000,
+};
+
+static const struct qcom_cc_desc lpass_audio_csr_reset_sc8280xp_desc = {
+ .config = &lpass_audio_csr_sc8280xp_regmap_config,
+ .resets = lpass_audio_csr_sc8280xp_resets,
+ .num_resets = ARRAY_SIZE(lpass_audio_csr_sc8280xp_resets),
+};
+
static const struct qcom_reset_map lpass_tcsr_sc8280xp_resets[] = {
[LPASS_AUDIO_SWR_TX_CGCR] = { 0xc010, 1 },
};
@@ -33,6 +53,9 @@ static const struct qcom_cc_desc lpass_tcsr_reset_sc8280xp_desc = {
static const struct of_device_id lpasscc_sc8280xp_match_table[] = {
{
+ .compatible = "qcom,sc8280xp-lpassaudiocc",
+ .data = &lpass_audio_csr_reset_sc8280xp_desc,
+ }, {
.compatible = "qcom,sc8280xp-lpasscc",
.data = &lpass_tcsr_reset_sc8280xp_desc,
},
--
2.25.1
