On 2023/4/13 16:41, Krzysztof Kozlowski wrote: > On 13/04/2023 04:34, Changhuang Liang wrote: >>>>>> + lane_maps: >>>>> >>>>> Why did this appear? Underscores are not allowed. It looks like you >>>>> re-implement some standard property. >>>>> >>>> >>>> Will change to lane-maps. >>>> Yes, according to Vinod advice, lane mapping table use device tree >>>> to parse makes sense. >>> >>> Hm, I have a feeling that I saw such property, so you should dig into >>> existing and in-flight bindings. >>> >>> Best regards, >>> Krzysztof >>> >> >> A standard property? Like "clocks" or "resets"? > > Like lane-polarities now submitted to one MIPI. > > Anyway it does not look like a property of a board. You said it is fixed > per SoC, so it should be implied from the compatible. Otherwise please > explain in description and provide some rationale. > > Best regards, > Krzysztof > This property is the only one used for this IP, I have compared this IP with other DPHY rx module, DPHY modules form the other manufacturers not have this configure. And we also have a SoC called JH7100. It DPHY rx module is the same as JH7110. But we don't do the upstream work on it. If it use this lane-maps will be configure as "lane_maps = /bits/ 8 <0 1 2 3 4 5>;". So what do you think? Can this configure be implemented into a property?
