On 12/04/2023 10:45, Changhuang Liang wrote: > StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on > a M31 IP. Add a binding for it. So this is D-PHY? Or the other patch is D-PHY? The naming is quite confusing and your commit msgs are not helping here. Also the power domain phandle here adds to the confusion. > > Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx> > --- > .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > > diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > new file mode 100644 > index 000000000000..5fb2f14af816 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive SoC MIPI D-PHY Rx Controller > + > +maintainers: > + - Jack Zhu <jack.zhu@xxxxxxxxxxxxxxxx> > + - Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx> > + > +description: > + The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer > + CSI camera data. > + > +properties: > + compatible: > + const: starfive,jh7110-dphy-rx > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: config clock > + - description: reference clock > + - description: escape mode transmit clock > + > + clock-names: > + items: > + - const: cfg > + - const: ref > + - const: tx > + > + resets: > + items: > + - description: DPHY_HW reset > + - description: DPHY_B09_ALWAYS_ON reset > + > + power-domains: > + maxItems: 1 > + > + lane_maps: Why did this appear? Underscores are not allowed. It looks like you re-implement some standard property. > + $ref: /schemas/types.yaml#/definitions/uint8-array > + description: > + D-PHY rx controller physical lanes and logic lanes mapping table. > + items: > + - description: logic lane index point to physical lane clock lane 0 > + - description: logic lane index point to physical lane data lane 0 > + - description: logic lane index point to physical lane data lane 1 > + - description: logic lane index point to physical lane data lane 2 > + - description: logic lane index point to physical lane data lane 3 > + - description: logic lane index point to physical lane clock lane 1 > + Best regards, Krzysztof
