On Mon, Feb 6, 2023 at 6:01 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> wrote: > > Changes in v3: > - Added commit to export register/unregister/parse FHCTL functions > to allow building clock drivers using FHCTL as modules > > Changes in v2: > - Rebased over v4 of my clock drivers cleanups series [1] > > This series adds support for Frequency Hopping (FHCTL) on more MediaTek > SoCs, specifically, MT6795, MT8173, MT8192 and MT8195. > > In order to support older platforms like MT6795 and MT8173 it was > necessary to add a new register layout that is ever-so-slightly > different from the one that was previously introduced for MT8186. > > Since the new layout refers to older SoCs, the one valid for MT8186 > and newer SoCs was renamed to be a "v2" layout, while the new one > for older chips gets the "v1" name. > > Note: These commits won't change any behavior unless FHCTL gets > explicitly enabled and configured in devicetrees. > > [1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=714059 > AngeloGioacchino Del Regno (7): > clk: mediatek: fhctl: Add support for older fhctl register layout > clk: mediatek: clk-pllfh: Export register/unregister/parse functions > dt-bindings: clock: mediatek,mt8186-fhctl: Support MT6795, > MT8173/92/95 > clk: mediatek: mt6795: Add support for frequency hopping through FHCTL > clk: mediatek: mt8173: Add support for frequency hopping through FHCTL > clk: mediatek: mt8192: Add support for frequency hopping through FHCTL > clk: mediatek: mt8195: Add support for frequency hopping through FHCTL The changes look good to me overall. I've asked MediaTek to take a look at the various parameters used is this series, as I don't have the register definitions for the old version, and from what I've been told, the slope and other parameters depend on the chip design as well as manufacturing process used. So, code wise this series is Reviewed-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
