The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add support for reading the OCOTP calibration
data and programming those into the TMU hardware.
The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4,
the programming differs in each case.
Based on U-Boot commits:
70487ff386c ("imx8mm: Load fuse for TMU TCALIV and TASR")
ebb9aab318b ("imx: load calibration parameters from fuse for i.MX8MP")
Signed-off-by: Marek Vasut <marex@xxxxxxx>
---
Cc: Adam Ford <aford173@xxxxxxxxx>
Cc: Alice Guo <alice.guo@xxxxxxx>
Cc: Amit Kucheria <amitk@xxxxxxxxxx>
Cc: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
Cc: Fabio Estevam <festevam@xxxxxxxxx>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx>
Cc: Li Jun <jun.li@xxxxxxx>
Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
Cc: Markus Niebel <Markus.Niebel@xxxxxxxxxxxxxxx>
Cc: NXP Linux Team <linux-imx@xxxxxxx>
Cc: Peng Fan <peng.fan@xxxxxxx>
Cc: Pengutronix Kernel Team <kernel@xxxxxxxxxxxxxx>
Cc: Rafael J. Wysocki <rafael@xxxxxxxxxx>
Cc: Richard Cochran <richardcochran@xxxxxxxxx>
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Cc: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Cc: Shawn Guo <shawnguo@xxxxxxxxxx>
Cc: Zhang Rui <rui.zhang@xxxxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
To: linux-pm@xxxxxxxxxxxxxxx
To: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
---
drivers/thermal/imx8mm_thermal.c | 163 +++++++++++++++++++++++++++++++
1 file changed, 163 insertions(+)
diff --git a/drivers/thermal/imx8mm_thermal.c b/drivers/thermal/imx8mm_thermal.c
index e2c2673025a7a..da09c00ac663a 100644
--- a/drivers/thermal/imx8mm_thermal.c
+++ b/drivers/thermal/imx8mm_thermal.c
@@ -10,6 +10,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
@@ -20,6 +21,22 @@
#define TER 0x0 /* TMU enable */
#define TPS 0x4
#define TRITSR 0x20 /* TMU immediate temp */
+/* TMU calibration data registers */
+#define TASR 0x28
+#define TASR_BUF_SLOPE_MASK GENMASK(19, 16)
+#define TASR_BUF_VREF_MASK GENMASK(4, 0) /* TMU_V1 */
+#define TASR_BUF_VERF_SEL_MASK GENMASK(1, 0) /* TMU_V2 */
+#define TCALIV(n) (0x30 + ((n) * 4))
+#define TCALIV_EN BIT(31)
+#define TCALIV_HR_MASK GENMASK(23, 16) /* TMU_V1 */
+#define TCALIV_RT_MASK GENMASK(7, 0) /* TMU_V1 */
+#define TCALIV_SNSR105C_MASK GENMASK(27, 16) /* TMU_V2 */
+#define TCALIV_SNSR25C_MASK GENMASK(11, 0) /* TMU_V2 */
+#define TRIM 0x3c
+#define TRIM_BJT_CUR_MASK GENMASK(23, 20)
+#define TRIM_BGR_MASK GENMASK(31, 28)
+#define TRIM_VLSB_MASK GENMASK(15, 12)
+#define TRIM_EN_CH BIT(7)
#define TER_ADC_PD BIT(30)
#define TER_EN BIT(31)
@@ -32,6 +49,25 @@
#define SIGN_BIT BIT(7)
#define TEMP_VAL_MASK GENMASK(6, 0)
+/* TMU OCOTP calibration data bitfields */
+#define ANA0_EN BIT(25)
+#define ANA0_BUF_VREF_MASK GENMASK(24, 20)
+#define ANA0_BUF_SLOPE_MASK GENMASK(19, 16)
+#define ANA0_HR_MASK GENMASK(15, 8)
+#define ANA0_RT_MASK GENMASK(7, 0)
+#define TRIM2_VLSB_MASK GENMASK(23, 20)
+#define TRIM2_BGR_MASK GENMASK(19, 16)
+#define TRIM2_BJT_CUR_MASK GENMASK(15, 12)
+#define TRIM2_BUF_SLOP_SEL_MASK GENMASK(11, 8)
+#define TRIM2_BUF_VERF_SEL_MASK GENMASK(7, 6)
+#define TRIM3_TCA25_0_LSB_MASK GENMASK(31, 28)
+#define TRIM3_TCA40_0_MASK GENMASK(27, 16)
+#define TRIM4_TCA40_1_MASK GENMASK(31, 20)
+#define TRIM4_TCA105_0_MASK GENMASK(19, 8)
+#define TRIM4_TCA25_0_MSB_MASK GENMASK(7, 0)
+#define TRIM5_TCA105_1_MASK GENMASK(23, 12)
+#define TRIM5_TCA25_1_MASK GENMASK(11, 0)
+
#define VER1_TEMP_LOW_LIMIT 10000
#define VER2_TEMP_LOW_LIMIT -40000
#define VER2_TEMP_HIGH_LIMIT 125000
@@ -128,6 +164,129 @@ static void imx8mm_tmu_probe_sel_all(struct imx8mm_tmu *tmu)
writel_relaxed(val, tmu->base + TPS);
}
+static int imx8mm_tmu_probe_set_calib_v1(struct platform_device *pdev,
+ struct imx8mm_tmu *tmu)
+{
+ struct device *dev = &pdev->dev;
+ u32 ana0;
+ int ret;
+
+ ret = nvmem_cell_read_u32(&pdev->dev, "calib", &ana0);
+ if (ret) {
+ dev_warn(dev, "Failed to read OCOTP nvmem cell (%d).\n", ret);
+ return ret;
+ }
+
+ writel(FIELD_PREP(TASR_BUF_VREF_MASK,
+ FIELD_GET(ANA0_BUF_VREF_MASK, ana0)) |
+ FIELD_PREP(TASR_BUF_SLOPE_MASK,
+ FIELD_GET(ANA0_BUF_SLOPE_MASK, ana0)),
+ tmu->base + TASR);
+
+ writel(FIELD_PREP(TCALIV_RT_MASK, FIELD_GET(ANA0_RT_MASK, ana0)) |
+ FIELD_PREP(TCALIV_HR_MASK, FIELD_GET(ANA0_HR_MASK, ana0)) |
+ ((ana0 & ANA0_EN) ? TCALIV_EN : 0),
+ tmu->base + TCALIV(0));
+
+ return 0;
+}
+
+static int imx8mm_tmu_probe_set_calib_v2(struct platform_device *pdev,
+ struct imx8mm_tmu *tmu)
+{
+ struct device *dev = &pdev->dev;
+ struct nvmem_cell *cell;
+ u32 trim[4] = { 0 };
+ size_t len;
+ void *buf;
+
+ cell = nvmem_cell_get(dev, "calib");
+ if (IS_ERR(cell))
+ return PTR_ERR(cell);
+
+ buf = nvmem_cell_read(cell, &len);
+ nvmem_cell_put(cell);
+
+ if (IS_ERR(buf))
+ return PTR_ERR(buf);
+
+ memcpy(trim, buf, min(len, sizeof(trim)));
+ kfree(buf);
+
+ if (len != 16) {
+ dev_err(dev,
+ "OCOTP nvmem cell length is %ld, must be 16.\n", len);
+ return -EINVAL;
+ }
+
+ /* Blank sample hardware */
+ if (!trim[0] && !trim[1] && !trim[2] && !trim[3]) {
+ /* Use a default 25C binary codes */
+ writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
+ tmu->base + TCALIV(0));
+ writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
+ tmu->base + TCALIV(1));
+ return 0;
+ }
+
+ writel(FIELD_PREP(TASR_BUF_VERF_SEL_MASK,
+ FIELD_GET(TRIM2_BUF_VERF_SEL_MASK, trim[0])) |
+ FIELD_PREP(TASR_BUF_SLOPE_MASK,
+ FIELD_GET(TRIM2_BUF_SLOP_SEL_MASK, trim[0])),
+ tmu->base + TASR);
+
+ writel(FIELD_PREP(TRIM_BJT_CUR_MASK,
+ FIELD_GET(TRIM2_BJT_CUR_MASK, trim[0])) |
+ FIELD_PREP(TRIM_BGR_MASK, FIELD_GET(TRIM2_BGR_MASK, trim[0])) |
+ FIELD_PREP(TRIM_VLSB_MASK, FIELD_GET(TRIM2_VLSB_MASK, trim[0])) |
+ TRIM_EN_CH,
+ tmu->base + TRIM);
+
+ writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
+ FIELD_GET(TRIM3_TCA25_0_LSB_MASK, trim[1]) |
+ (FIELD_GET(TRIM4_TCA25_0_MSB_MASK, trim[2]) << 4)) |
+ FIELD_PREP(TCALIV_SNSR105C_MASK,
+ FIELD_GET(TRIM4_TCA105_0_MASK, trim[2])),
+ tmu->base + TCALIV(0));
+
+ writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
+ FIELD_GET(TRIM5_TCA25_1_MASK, trim[3])) |
+ FIELD_PREP(TCALIV_SNSR105C_MASK,
+ FIELD_GET(TRIM5_TCA105_1_MASK, trim[3])),
+ tmu->base + TCALIV(1));
+
+ writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
+ FIELD_GET(TRIM3_TCA40_0_MASK, trim[1])) |
+ FIELD_PREP(TCALIV_SNSR105C_MASK,
+ FIELD_GET(TRIM4_TCA40_1_MASK, trim[2])),
+ tmu->base + TCALIV(2));
+
+ return 0;
+}
+
+static int imx8mm_tmu_probe_set_calib(struct platform_device *pdev,
+ struct imx8mm_tmu *tmu)
+{
+ struct device *dev = &pdev->dev;
+
+ /*
+ * Lack of calibration data OCOTP reference is not considered
+ * fatal to retain compatibility with old DTs. It is however
+ * strongly recommended to update such old DTs to get correct
+ * temperature compensation values for each SoC.
+ */
+ if (!of_find_property(pdev->dev.of_node, "nvmem-cells", NULL)) {
+ dev_warn(dev,
+ "No OCOTP nvmem reference found, SoC-specific calibration not loaded. Please update your DT.\n");
+ return 0;
+ }
+
+ if (tmu->socdata->version == TMU_VER1)
+ return imx8mm_tmu_probe_set_calib_v1(pdev, tmu);
+
+ return imx8mm_tmu_probe_set_calib_v2(pdev, tmu);
+}
+
static int imx8mm_tmu_probe(struct platform_device *pdev)
{
const struct thermal_soc_data *data;
@@ -180,6 +339,10 @@ static int imx8mm_tmu_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, tmu);
+ ret = imx8mm_tmu_probe_set_calib(pdev, tmu);
+ if (ret)
+ goto disable_clk;
+
/* enable all the probes for V2 TMU */
if (tmu->socdata->version == TMU_VER2)
imx8mm_tmu_probe_sel_all(tmu);
--
2.35.1
