[AMD Official Use Only - General] > -----Original Message----- > From: Borislav Petkov <bp@xxxxxxxxx> > Sent: Wednesday, November 9, 2022 12:38 AM > To: Datta, Shubhrajyoti <shubhrajyoti.datta@xxxxxxx> > Cc: linux-edac@xxxxxxxxxxxxxxx; git (AMD-Xilinx) <git@xxxxxxx>; > devicetree@xxxxxxxxxxxxxxx; michal.simek@xxxxxxxxxx; rric@xxxxxxxxxx; > james.morse@xxxxxxx; tony.luck@xxxxxxxxx; mchehab@xxxxxxxxxx; > robh+dt@xxxxxxxxxx; krzysztof.kozlowski@xxxxxxxxxx > Subject: Re: [PATCH v2 0/2] edac: xilinx: Added EDAC support for Xilinx DDR > controller > > Caution: This message originated from an External Source. Use proper > caution when opening attachments, clicking links, or responding. > > > On Mon, Nov 07, 2022 at 11:54:11AM +0530, Shubhrajyoti Datta wrote: > > > > The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and > > LPDDR4/4X memory interfaces. It has four programmable NoC interface > > ports and is designed to handle multiple streams of traffic. > > > > Optional external interface reliability include ECC error > > detection/correction and command address parity. > > > > Adding edac support for DDR Memory controller. > > Same question as in > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore. > kernel.org%2Fr%2FY2qiRoiYepte%2FR4W%40zn.tnic&data=05%7C01%7 > Cshubhrajyoti.datta%40amd.com%7C5caa7f12a7ca4ede4b5e08dac1bc8ea7% > 7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C638035312878146800 > %7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiL > CJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=3%2B4 > KXoDza2kloKAWI27LT5VvZqQ5DQQMJm91s%2F5%2FrtQ%3D&reserved > =0 > > How many memory controllers are there in Xilinx boards and how many > EDAC drivers can potentially be needed to run in parallel? Platform | Drivers / Controllers | ------------------------------------------------------------ ZynqMP | Synopsys and OCM | Versal | DDRMC and OCM | > > Also, this is an integrated memory controller, ZynqMP OCM is a on-chip > controller. Can we have a single xilinx_edac driver which contains support for > both memory controller types or are they completely different? This patch series is for Xilinx Versal platform targeting DDR Memory controller. As they are two different memory controllers (DDRMC and OCM) on different platforms (Versal and ZynqMP), so we cannot have a single driver. > > Thx. > > -- > Regards/Gruss, > Boris. > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpeo > ple.kernel.org%2Ftglx%2Fnotes-about- > netiquette&data=05%7C01%7Cshubhrajyoti.datta%40amd.com%7C5caa > 7f12a7ca4ede4b5e08dac1bc8ea7%7C3dd8961fe4884e608e11a82d994e183d% > 7C0%7C0%7C638035312878146800%7CUnknown%7CTWFpbGZsb3d8eyJWIjoi > MC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C300 > 0%7C%7C%7C&sdata=JjvQZVXXAfJPS5tOj87QYzUdFhqzuZ3pO9Q%2BkQ > 2IhTU%3D&reserved=0
