On Mon, Nov 07, 2022 at 11:54:11AM +0530, Shubhrajyoti Datta wrote: > > The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/4X > memory interfaces. It has four programmable NoC interface ports and is designed > to handle multiple streams of traffic. > > Optional external interface reliability include ECC error detection/correction > and command address parity. > > Adding edac support for DDR Memory controller. Same question as in https://lore.kernel.org/r/Y2qiRoiYepte/R4W@xxxxxxx How many memory controllers are there in Xilinx boards and how many EDAC drivers can potentially be needed to run in parallel? Also, this is an integrated memory controller, ZynqMP OCM is a on-chip controller. Can we have a single xilinx_edac driver which contains support for both memory controller types or are they completely different? Thx. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette
