D1 contains a pin controller similar to previous SoCs, but with some
register layout changes. It includes 6 interrupt-capable pin banks.
D1s is a low pin count version of the D1 SoC, with some pins omitted.
The remaining pins have the same function assignments as D1.
Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx>
---
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index bfce850c2035..3da52814f151 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -46,6 +46,8 @@ properties:
- allwinner,sun8i-v3s-pinctrl
- allwinner,sun9i-a80-pinctrl
- allwinner,sun9i-a80-r-pinctrl
+ - allwinner,sun20i-d1-pinctrl
+ - allwinner,sun20i-d1s-pinctrl
- allwinner,sun50i-a64-pinctrl
- allwinner,sun50i-a64-r-pinctrl
- allwinner,sun50i-a100-pinctrl
@@ -171,6 +173,19 @@ allOf:
minItems: 7
maxItems: 7
+ - if:
+ properties:
+ compatible:
+ enum:
+ - allwinner,sun20i-d1-pinctrl
+ - allwinner,sun20i-d1s-pinctrl
+
+ then:
+ properties:
+ interrupts:
+ minItems: 6
+ maxItems: 6
+
- if:
properties:
compatible:
--
2.35.1
