On 26/06/2022 04:11, Samuel Holland wrote: > D1 contains a pin controller similar to previous SoCs, but with some > register layout changes. It includes 6 interrupt-capable pin banks. > > D1s is a low pin count version of the D1 SoC, with some pins omitted. > The remaining pins have the same function assignments as D1. > > Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
