On Sun, Jun 26, 2022 at 4:11 AM Samuel Holland <samuel@xxxxxxxxxxxx> wrote: > D1 contains a pin controller similar to previous SoCs, but with some > register layout changes. It includes 6 interrupt-capable pin banks. > > D1s is a low pin count version of the D1 SoC, with some pins omitted. > The remaining pins have the same function assignments as D1. > > Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx> All 6 patches applied to the pinctrl tree, the last patch 6/6 required some fuzzing so please check the result! Yours, Linus Walleij
