From: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
Create new property for (rockchip) PCIe controller binding to
define lane mapping.
Rockchip driver uses this for bifurcation (true/false) based
on lanes should be splitted across controllers or not.
On rk3568 there are 2 PCIe Controllers which share 2 PCIe lanes.
pcie3x1: pcie@fe270000 //lane1 when using 1+1
pcie3x2: pcie@fe280000 //lane0 when using 1+1
This ends up in one Controller (pcie3x1) uses lane-map = <0 1>; and
the other lane-map = <1 0>; (pcie3x2)
This means there are 2 lanes (count of numbers), one (by position)
is mapped to the first controller, the other one is used on the other
controller.
In rockchip PCIe driver the lane-map is simply converted to the
bifurcation bool instead of direct mapping a specific lane to a
controller.
There is not yet any slot mapping below one controller.
But for binding this may be possible like:
lane-map = <1 2 3 3 4 4 4 4>;
| | | ...
lane0 | |
lane1 |
lane2
on a 8-lane phy.
This can map lane0 to port1 (number used at this position),
lane1 to port2, lanes 2+3 to port 3 and lanes 4,5,6,7 to port 4.
Signed-off-by: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
---
v2:
- new patch
---
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
index a992970e8b85..998b20b3a9dc 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -52,6 +52,8 @@ properties:
- const: pclk
- const: aux
+ lane-map: true
+
msi-map: true
num-lanes: true
@@ -74,8 +76,6 @@ properties:
reset-names:
const: pipe
- bifurcation: true
-
vpcie3v3-supply: true
required:
@@ -115,6 +115,7 @@ examples:
"aclk_dbi", "pclk",
"aux";
device_type = "pci";
+ lane-map = <0 1>;
linux,pci-domain = <2>;
max-link-speed = <2>;
msi-map = <0x2000 &its 0x2000 0x1000>;
--
2.25.1
