From: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx> Add constants that can be used in devicetree and driver for PCIe v3 phy. Signed-off-by: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx> --- v2: - new patch because splitting out this file - rename file from snps to rockchip --- include/dt-bindings/phy/phy-rockchip-pcie3.h | 21 ++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 include/dt-bindings/phy/phy-rockchip-pcie3.h diff --git a/include/dt-bindings/phy/phy-rockchip-pcie3.h b/include/dt-bindings/phy/phy-rockchip-pcie3.h new file mode 100644 index 000000000000..93e57edd337d --- /dev/null +++ b/include/dt-bindings/phy/phy-rockchip-pcie3.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _DT_BINDINGS_PHY_ROCKCHIP_PCIE3 +#define _DT_BINDINGS_PHY_ROCKCHIP_PCIE3 + +/* + * pcie30_phy_mode[2:0] + * bit2: aggregation + * bit1: bifurcation for port 1 + * bit0: bifurcation for port 0 + */ +#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */ +#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */ +#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */ +#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */ +#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */ + +#endif /* _DT_BINDINGS_PHY_ROCKCHIP_PCIE3 */ -- 2.25.1
