+ Bhaskar
On Thu, Apr 08, 2021 at 01:02:18PM +0200, Michael Walle wrote:
> While enabling EDAC support for the LS1028A it was discovered that the
> memory node has a wrong endianness setting as well as a wrong interrupt
> assignment. Fix both.
>
> This was tested on a sl28 board. To force ECC errors, you can use the
> error injection supported by the controller in hardware (with
> CONFIG_EDAC_DEBUG enabled):
>
> # enable error injection
> $ echo 0x100 > /sys/devices/system/edac/mc/mc0/inject_ctrl
> # flip lowest bit of the data
> $ echo 0x1 > /sys/devices/system/edac/mc/mc0/inject_data_lo
>
> Fixes: 8897f3255c9c ("arm64: dts: Add support for NXP LS1028A SoC")
> Signed-off-by: Michael Walle <michael@xxxxxxxx>
Bhaskar,
Does it look good to you?
Shawn
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 9506f0669ead..040a3e529bf1 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -197,8 +197,8 @@
> ddr: memory-controller@1080000 {
> compatible = "fsl,qoriq-memory-controller";
> reg = <0x0 0x1080000 0x0 0x1000>;
> - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> - big-endian;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + little-endian;
> };
>
> dcfg: syscon@1e00000 {
> --
> 2.20.1
>
