Hi all, I'm writing a clock driver for a PLL unit in an ARM SoC that I hope to wrap up and send the patches for in the next few days. This PLL unit has one PLL and then a series of dividers. Then each divider apparently has between 0 and 3 dividers coming off of it. As there is no documentation for this thing and I'm not sure what the logical output numbers are or even if I know all of them I was considering making the number of clock cells 2 and having the first be the first divider (i.e. the divide by 2 output would be 2) and the second cell the chained divider or 0 for no divider. If I should just decide the order of the outputs and come up with indexes for them would it still be ok to nest them like the first cell is the index of the divider and then the second cell is the index of the chained divider? Thanks, Daniel
