Re: Acceptable format for clock cells.

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Quoting Daniel Palmer (2020-10-30 04:52:31)
> Hi all,
> 
> I'm writing a clock driver for a PLL unit in an ARM SoC that I hope to
> wrap up and send the patches for in the next few days.
> 
> This PLL unit has one PLL and then a series of dividers. Then each
> divider apparently has between 0 and 3 dividers coming off of it.
> 
> As there is no documentation for this thing and I'm not sure what the
> logical output numbers are or even if I know all of them I was
> considering making the number of clock cells 2 and having the first be
> the first divider (i.e. the divide by 2 output would be 2) and the
> second cell the chained divider or 0 for no divider.

Does the PLL need to be expressed anywhere in the binding?

> 
> If I should just decide the order of the outputs and come up with
> indexes for them would it still be ok to nest them like the first cell
> is the index of the divider and then the second cell is the index of
> the chained divider?
> 

Generally we try to encourage one-cell or zero-cell bindings because
they're simple. A two cell binding is possible if you really want but
I'd say do a one-cell binding and make up some numbering scheme for the
different clks. A one cell binding also makes it easy to populate an
array of clk_hw pointers that the DT xlate function can pick from. When
it gets to two cells or more it gets complicated, but still doable.

It would be great if clk hardware started numbering the clks instead of
naming them specific names but this almost never happens. It would
certainly make life easier if the datasheet said "Use clk #25 for the
uart" but usually SoC hardware engineers give them names and don't
consider a pinout scheme. I'd say this is mostly because the engineers
control the connections between their clk controller and the consumers.

Finally, if you don't have a datasheet then think about the person who
has to write the DT. Are they going to know the details of the clk tree
inside the PLL unit to know that they need the third divider underneath
the second divider? Or are they going to know they need the "uart clk"
and that can be some friendly #define that hides this detail from them?




[Index of Archives]     [Device Tree Compilter]     [Device Tree Spec]     [Linux Driver Backports]     [Video for Linux]     [Linux USB Devel]     [Linux PCI Devel]     [Linux Audio Users]     [Linux Kernel]     [Linux SCSI]     [XFree86]     [Yosemite Backpacking]


  Powered by Linux