On 04/01/2020 10:04, Maxime Ripard wrote:
Hi,
> On Thu, Jan 02, 2020 at 10:41:58AM +0000, Andre Przywara wrote:
>> On Thu, 2 Jan 2020 10:57:11 +0100
>> Maxime Ripard <mripard@xxxxxxxxxx> wrote:
>>> On Thu, Jan 02, 2020 at 01:26:57AM +0000, Andre Przywara wrote:
>>>> The Allwinner R40 SoC contains four SPI controllers, using the newer
>>>> sun6i design (but at the legacy addresses).
>>>> The controller seems to be fully compatible to the A64 one, so no driver
>>>> changes are necessary.
>>>> The first three controller can be used on two sets of pins, but SPI3 is
>>>> only routed to one set on Port A.
>>>>
>>>> Tested by connecting a SPI flash to a Bananapi M2 Berry on the SPI0
>>>> PortC header pins.
>>>>
>>>> Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
>>>> ---
>>>> arch/arm/boot/dts/sun8i-r40.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++
>>>> 1 file changed, 89 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
>>>> index 8dcbc4465fbb..af437391dcf4 100644
>>>> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
>>>> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
>>>> @@ -418,6 +418,41 @@
>>>> bias-pull-up;
>>>> };
>>>>
>>>> + spi0_pc_pins: spi0-pc-pins {
>>>> + pins = "PC0", "PC1", "PC2", "PC23";
>>>> + function = "spi0";
>>>> + };
>>>> +
>>>> + spi0_pi_pins: spi0-pi-pins {
>>>> + pins = "PI10", "PI11", "PI12", "PI13", "PI14";
>>>> + function = "spi0";
>>>> + };
>>>
>>> This split doesn't really work though :/
>>>
>>> The PC pins group has MOSI, MISO, CLK and CS0, while the PI pins group
>>> has CS0, CLK, MOSI, MISO and CS1.
>>>
>>> Meaning that if a board uses a GPIO CS pin, we can't really express
>>> that
>>
>> Does that actually work? I dimly remember checking our sunxi driver
>> a while ago and I wasn't sure that would be functional there.
>
> It's something generic that should be handled by the core iirc. We
> might be missing the few things to enable it though, but that's
> irrelevant to the DT itself.
Agreed, I just remembered that I checked this a while ago and found that
we always control the SS_LEVEL bit, but never anything else. But indeed
irrelevant for this.
>
>>> and any board using the PI pins for its SPI bus will try to
>>> claim CS0 and CS1, no matter how many devices are connected on the bus
>>> (and if there's one, there might be something else connected to PI14).
>>
>> True.
>>
>>> And you can't have a board using CS1 with the PC signals either.
>>>
>>> You should split away the CS pins into separate groups, like we're
>>> doing with the A20 for example.
>>
>> Ah, yeah, makes sense, thanks for the pointer.
>>
>>> And please add /omit-if-no-ref/ to those groups.
>>
>> I was a bit reluctant to do this:
>>
>> First there does not seem to be any good documentation about it,
>> neither in the official DT spec nor in dtc, even though I think I
>> understand what it does ;-)
>
> If a node doesn't have a phandle pointing to it, it will be ignored at
> compilation time.
That's what I figured ;-)
>> Second it seems to break in U-Boot atm. Looks like applying your dtc
>> patch fixes that, though. Do you know if U-Boot allows
>> cherry-picking dtc patches? If yes, I could post your patch.
>
> I know I did it for libfdt at some point, so I guess dtc would work
> too, but I'm not really sure. Rockchip is also using it iirc, so
> there's interest in supporting it in U-Boot anyway.
OK, will post it.
>> But more importantly: what are the guidelines for using this tag? I
>> understand the desire to provide every possible pin description on
>> one hand, but wanting to avoid having *all of them* in *each* .dtb
>> on the other.
>
> Pin groups will take a lot of space in the dtb, and the DT parsing
> will take some measurable time,
Really? Where is that? In Linux, or in U-Boot, possibly with the caches
off? I am just curious. AFAIK there are some inefficient algorithms in
libfdt (which trade performance for a smaller memory footprint), but I
thought those would be called only very rarely.
> so if we can get rid of the unused pin
> groups, that's great :)
I see it is preferable over creating a separate copy of the .dts file.
>> But how does this play along with overlays? Shouldn't at least those
>> interface pins that are exposed on headers stay in each .dtb? Can we
>> actually make this decision in the SoC .dtsi file?
>
> If the DT is compiled with overlays, that property is ignored iirc and
> the node will be output in the compiled DT, because while if you don't
> have overlays support you can tell if something points to that node,
> you can't with overlays since those references might be stored
> elsewhere.
Yeah, Chen-Yu mentioned that already. Thanks for the info, I missed that.
>> And should there be a dtc command line option to ignore those tags,
>> or even to apply this tag (virtually) to every node?
>
> Most of the nodes are (reference) leaves in a DT though. Pretty much
> all the device nodes have no references pointing to them, just like
> most of the buses, the CPU nodes, etc. And I'm pretty sure you want to
> keep them :)
Yeah, that was a New-Year's brain-fart of mine ;-)
While I was changing the patch I figured that it gets quite lengthy.
Also looking at the a20.dtsi, I see that *all* pin groups have this tag
now. Wouldn't it be easier to introduce *one* tag that applies that to
all children of a node?
Another thing I was wondering about: Would we gain something by not
compiling nodes which have status = "disabled"? This is mentioned as a
generic property in the DT spec, although it says there that the exact
meaning is device dependent. But it sound still worthwhile, especially
since we would avoid more pin groups to be compiled in.
Cheers,
Andre.
