Hi,
On Thu, Jan 02, 2020 at 01:26:57AM +0000, Andre Przywara wrote:
> The Allwinner R40 SoC contains four SPI controllers, using the newer
> sun6i design (but at the legacy addresses).
> The controller seems to be fully compatible to the A64 one, so no driver
> changes are necessary.
> The first three controller can be used on two sets of pins, but SPI3 is
> only routed to one set on Port A.
>
> Tested by connecting a SPI flash to a Bananapi M2 Berry on the SPI0
> PortC header pins.
>
> Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
> ---
> arch/arm/boot/dts/sun8i-r40.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index 8dcbc4465fbb..af437391dcf4 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -418,6 +418,41 @@
> bias-pull-up;
> };
>
> + spi0_pc_pins: spi0-pc-pins {
> + pins = "PC0", "PC1", "PC2", "PC23";
> + function = "spi0";
> + };
> +
> + spi0_pi_pins: spi0-pi-pins {
> + pins = "PI10", "PI11", "PI12", "PI13", "PI14";
> + function = "spi0";
> + };
This split doesn't really work though :/
The PC pins group has MOSI, MISO, CLK and CS0, while the PI pins group
has CS0, CLK, MOSI, MISO and CS1.
Meaning that if a board uses a GPIO CS pin, we can't really express
that, and any board using the PI pins for its SPI bus will try to
claim CS0 and CS1, no matter how many devices are connected on the bus
(and if there's one, there might be something else connected to PI14).
And you can't have a board using CS1 with the PC signals either.
You should split away the CS pins into separate groups, like we're
doing with the A20 for example.
And please add /omit-if-no-ref/ to those groups.
Thanks!
Maxime
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