In some place in the driver regmap_update_bits was misused. Indeed the
last argument is not the value of the bit (or group of bits) itself but
the mask value inside the register.
So when setting the bit N, then the value must be BIT(N) and not 1.
CC: Chris Packham <Chris.Packham@xxxxxxxxxxxxxxxxxxx>
CC: Ralph Sennhauser <ralph.sennhauser@xxxxxxxxx>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxxxxxxxxx>
Tested-by: Ralph Sennhauser <ralph.sennhauser@xxxxxxxxx>
Tested-by: Chris Packham <Chris.Packham@xxxxxxxxxxxxxxxxxxx>
Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxxxxxxxxx>
---
drivers/gpio/gpio-mvebu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 4aec8762fdc5..d5939913d310 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -341,7 +341,7 @@ static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
return ret;
regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
- BIT(pin), 1);
+ BIT(pin), BIT(pin));
return 0;
}
@@ -503,7 +503,7 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_LEVEL_LOW:
regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
- BIT(pin), 1);
+ BIT(pin), BIT(pin));
break;
case IRQ_TYPE_EDGE_BOTH: {
u32 data_in, in_pol, val;
--
git-series 0.9.1
--
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