On Tue, Jan 31, 2017 at 11:09:24AM +0100, Philipp Zabel wrote: > On Mon, 2017-01-30 at 13:06 +0000, Russell King - ARM Linux wrote: > > To help illustrate my point, consider the difference between > > MEDIA_BUS_FMT_RGB565_1X16 and MEDIA_BUS_FMT_RGB565_2X8_BE or > > MEDIA_BUS_FMT_RGB565_2X8_LE. RGB565_1X16 means 1 pixel over an effective > > 16-bit wide bus (if it's not 16-bit, then it has to be broken up into > > separate "samples".) RGB565_2X8 means 1 pixel as two 8-bit samples. > > > > So, the 10-bit bayer is 1 pixel as 1.25 bytes. Or is it, over a serial > > bus. Using the RGB565 case, 10-bit bayer over a 4 lane CSI bus becomes > > interesting: > > > > first byte 2nd 3rd > > lane 1 P0 9:2 S0 P7 9:2 > > lane 2 P1 9:2 P4 9:2 S1 > > lane 3 P2 9:2 P5 9:2 P8 9:2 > > lane 4 P3 9:2 P6 9:2 P9 9:2 > > > > S0 = P0/P1/P2/P3 least significant two bits > > S1 = P4/P5/P6/P7 least significant two bits > > > > or 2 lane CSI: > > first byte 2nd 3rd 4th 5th > > lane 1 P0 9:2 P2 S0 P5 P7 > > lane 2 P1 9:2 P3 P4 P6 S1 > > > > or 1 lane CSI: > > lane 1 P0 P1 P2 P3 S0 P4 P5 P6 P7 S1 P8 P9 ... > > These do look like three different media bus formats to me. This isn't limited to the serial side - the parallel bus side between the CSI2 interface and CSI2IPU wrapper, and the CSI2IPU wrapper and the CS0/1 interfaces is much the same with 10-bit bayer. Think of the CSI2 <-> CSI2IPU bit as the 4-lane case, lane 0 ending up on the least significant 8 bits of the 32-bit bus, lane 3 on the top 8-bits. Post CSI2IPU, it talks about a 16-bit bus in the diagrams, so that's kind of the 2-lane case above... -- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
