On Mon, 7 Mar 2016 12:02:02 +0200 Roger Quadros <rogerq@xxxxxx> wrote: > Hi Boris, > > On 07/03/16 11:34, Boris Brezillon wrote: > > Hi Roger, > > > > On Fri, 19 Feb 2016 23:15:35 +0200 > > Roger Quadros <rogerq@xxxxxx> wrote: > > > >> OMAPs can have 2 to 4 WAITPINs that can be used as general purpose > >> input if not used for memory wait state insertion. > >> > >> The first user will be the OMAP NAND chip to get the NAND > >> read/busy status using gpiolib. > > > > Just a comment on this approach. Why do you need to exposed native R/B > > pins as GPIOs? I mean, other NAND controllers are supporting R/B > > detection using dedicated logic, and they do not exposed those pins a > > plain GPIOs. Have you considered adding another property (rb-native ?) > > to deal with this case instead of emulating a GPIO controller? > > Side note: I added an rb-gpios property in my sunxi-nand DT binding > > because in some cases, the board design forces us to use a plain GPIO. > > OMAPs can have more than one WAITpins which can be used in multiple ways > - wait state insertion > - general purpose input > - edge detect interrupt > > It is not automatically tied to NAND read/busy# mechanism and needs software > to get the read/busy# state. > The register to get WAIT pin status is not situated in the NAND controller > register space but in the parent GPMC controller space. > > So we've modelled the WAIT pins as irqchip and gpiochip and users can > use them as they want. Okay. Thanks for the detailed explanation. -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
