On Thursday 09 April 2009 13:00:14 Nikula Jarkko (Nokia-D/Helsinki) wrote: > On Thu, 9 Apr 2009 11:34:41 +0200 > > "Ujfalusi Peter (Nokia-D/Tampere)" <peter.ujfalusi@xxxxxxxxx> wrote: > > - case SND_SOC_DAIFMT_DSP_B: > > + case SND_SOC_DAIFMT_DSP_A: > > /* 0-bit data delay */ > > regs->rcr2 |= RDATDLY(0); > > regs->xcr2 |= XDATDLY(0); > > -- > > Are you absolutely sure on this? According to WM9713, it's the DSP_A > where MSB is valid after 1 bit clock period of the FS. I think this is correct. The data is going to be valid exactly the same way, as the WM9713 data sheet describes. As for the DSP_B mode: I think it can be implemented like this: Invert the frame sync polarity, Then: case SND_SOC_DAIFMT_DSP_B: regs->srgr2 |= FPER(wlen * channels - 1); regs->srgr1 |= FWID(0); /* FS pulse width is 1 */ break; So the MSB will be in the correct place. -- Péter _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
