Hello Miquel, > Hi Amit, > > > > > > > For implementing this the current DT binding need to be > > > > > > updated as follows. > > > > > > > > > > So you want to go back to step 1 and redefine bindings? Is that worth? > > > > > > > > The current bindings are effective if we only support identical > > > > flash devices or flashes of the same make but with different sizes > > > > connected in stacked mode. However, if we want to extend stacked > > > > support to include flashes of different makes in stacked mode, > > > > > > The only actual feature the stacked mode brings is the ability to > > > consider two devices like one. This is abstracted by hardware, this is a > controller capability. > > > > Stacked mode is a software abstraction rather than a controller > > feature or capability. At any given time, the controller communicates > > with one of the two connected flash devices, as determined by the > > requested address and data length. If an operation starts on one flash > > and ends on the other, the core needs to split it into two separate > > operations and adjust the data length accordingly. > > I'm sorry, that was not my understanding, cf the initial RFC: > > Subject: [RFC PATCH 0/3] Dual stacked/parallel memories bindings > Date: Fri, 12 Nov 2021 16:24:08 +0100 > > "[...] supporting specific SPI controller modes like Xilinx's > where the controller can highly abstract the hardware and > provide access to a single bigger device instead [...]" > > Furthermore, I rapidly checked the Zynq7000 TRM, it suggests that the > controller is capable of addressing the right memory itself based on the > address, especially in linear mode? Yes, this is true only when operating in Linear Mode. In this mode, the Zynq 7000 can only perform read operations. Erase and write operations are possible only in I/O mode, so while operating in I/O mode the CS pins must be manually asserted by the driver according to the address and data length > > https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Dual-SS- > 4-bit-Stacked-I/O > > "The lower SPI flash memory should always be connected if the > linear Quad-SPI memory subsystem is used, and the upper flash > memory is optional. Total address space is 32 MB with a 25-bit > address. In IO mode, the MSB of the address is defined by > U_PAGE which is located at bit 28 of register 0xA0 . In Linear > address mode, AXI address bit 24 determines the upper or lower > memory page. All of the commands will be executed by the device > selected by U_PAGE in I/O mode and address bit 24 in linear > mode." > > Anyway, you may decide to go down the "pure software" route, which is > probably easier from an implementation perspective, but means you're > gonna have to argue -again- in favor of the representation of a purely virtual > device that is not hardware. Yes, that's correct, but I was planning to manage it through a new layer rather than using mtd-concat. As Tudor mentioned, I will start a new email thread outlining my proposal so we can resume the discussion on the patch moving forward. Regards, Amit > > Cheers, > Miquèl
