Hello Tudor, > -----Original Message----- > From: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> > Sent: Friday, December 15, 2023 1:40 PM > To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@xxxxxxx>; > broonie@xxxxxxxxxx; pratyush@xxxxxxxxxx; miquel.raynal@xxxxxxxxxxx; > richard@xxxxxx; vigneshr@xxxxxx; sbinding@xxxxxxxxxxxxxxxxxxxxx; > lee@xxxxxxxxxx; james.schulman@xxxxxxxxxx; david.rhodes@xxxxxxxxxx; > rf@xxxxxxxxxxxxxxxxxxxxx; perex@xxxxxxxx; tiwai@xxxxxxxx > Cc: linux-spi@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > michael@xxxxxxxx; linux-mtd@xxxxxxxxxxxxxxxxxxx; > nicolas.ferre@xxxxxxxxxxxxx; alexandre.belloni@xxxxxxxxxxx; > claudiu.beznea@xxxxxxxxx; Simek, Michal <michal.simek@xxxxxxx>; linux- > arm-kernel@xxxxxxxxxxxxxxxxxxx; alsa-devel@xxxxxxxxxxxxxxxx; > patches@xxxxxxxxxxxxxxxxxxxxx; linux-sound@xxxxxxxxxxxxxxx; git (AMD- > Xilinx) <git@xxxxxxx>; amitrkcian2002@xxxxxxxxx > Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support > in spi-nor > > > > On 15.12.2023 09:55, Mahapatra, Amit Kumar wrote: > >> Thanks! Can you share with us what flashes you used for testing in > >> the stacked and parallel configurations? > > I used SPI-NOR QSPI flashes for testing stacked and parallel. > > I got that, I wanted the flash name or device ID. N25Q00A, MX66U2G45G, IS25LP01G & W25H02JV are some of the QSPI flashes on which we tested. Additionally, we conducted tests on over 30 different QSPI flashes from four distinct vendors (Miron, Winbond, Macronix, and ISSI). > What I'm interested is if each flash is in its own package. Are they? I'm sorry, but I don't quite understand what you mean by "if each flash in its own package." > > > > >>>> can combine a SPI NOR with a SPI NAND in stacked configuration? > >>> No, Xilinx/AMD QSPI controllers doesn't support this configuration. > >>> > >> 2 SPI NANDs shall work with the AMD controller, right? > > We never tested 2 SPI-NAND with AMD controller. > > I was asking because I think the stacked layer shall be SPI MEM generic, and > not particular to SPI NOR. Yes, I agree. > > >> I skimmed over the QSPI controller datasheet and wondered why one > >> would get complicated with 2 Quad Flashes when we have Octal. But > >> then I saw that the same SoC can configure an Octal controller (the > >> Octal and Quad controllers seems mutual exclusive) and that the Octal > >> one can operate 2 octal flashes in stacked mode 🙂. > > Thats correct . > > > > Please let me know how you want me to proceed on this. > > I got you. Still need to allocate more time on this. Sure. Regards, Amit > > Cheers, > ta
