On 15.12.2023 09:55, Mahapatra, Amit Kumar wrote: >> Thanks! Can you share with us what flashes you used for testing in the >> stacked and parallel configurations? > I used SPI-NOR QSPI flashes for testing stacked and parallel. I got that, I wanted the flash name or device ID. What I'm interested is if each flash is in its own package. Are they? > >>>> can combine a SPI NOR with a SPI NAND in stacked configuration? >>> No, Xilinx/AMD QSPI controllers doesn't support this configuration. >>> >> 2 SPI NANDs shall work with the AMD controller, right? > We never tested 2 SPI-NAND with AMD controller. I was asking because I think the stacked layer shall be SPI MEM generic, and not particular to SPI NOR. >> I skimmed over the QSPI controller datasheet and wondered why one would >> get complicated with 2 Quad Flashes when we have Octal. But then I saw that >> the same SoC can configure an Octal controller (the Octal and Quad >> controllers seems mutual exclusive) and that the Octal one can operate 2 >> octal flashes in stacked mode 🙂. > Thats correct . > > Please let me know how you want me to proceed on this. I got you. Still need to allocate more time on this. Cheers, ta
