Hello Tudor, > -----Original Message----- > From: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> > Sent: Friday, February 9, 2024 4:36 PM > To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@xxxxxxx>; > broonie@xxxxxxxxxx; pratyush@xxxxxxxxxx; miquel.raynal@xxxxxxxxxxx; > richard@xxxxxx; vigneshr@xxxxxx; sbinding@xxxxxxxxxxxxxxxxxxxxx; > lee@xxxxxxxxxx; james.schulman@xxxxxxxxxx; david.rhodes@xxxxxxxxxx; > rf@xxxxxxxxxxxxxxxxxxxxx; perex@xxxxxxxx; tiwai@xxxxxxxx > Cc: linux-spi@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > michael@xxxxxxxx; linux-mtd@xxxxxxxxxxxxxxxxxxx; > nicolas.ferre@xxxxxxxxxxxxx; alexandre.belloni@xxxxxxxxxxx; > claudiu.beznea@xxxxxxxxx; Simek, Michal <michal.simek@xxxxxxx>; linux- > arm-kernel@xxxxxxxxxxxxxxxxxxx; alsa-devel@xxxxxxxxxxxxxxxx; > patches@xxxxxxxxxxxxxxxxxxxxx; linux-sound@xxxxxxxxxxxxxxx; git (AMD- > Xilinx) <git@xxxxxxx>; amitrkcian2002@xxxxxxxxx; Conor Dooley > <conor.dooley@xxxxxxxxxxxxx>; beanhuo@xxxxxxxxxx > Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support > in spi-nor > > CAUTION: This message has originated from an External Source. Please use > proper judgment and caution when opening attachments, clicking links, or > responding to this email. > > > On 12/21/23 06:54, Mahapatra, Amit Kumar wrote: > >> Something else to consider: I see that Micron has a twin quad mode: > >> https://media-www.micron.com/- > >> /media/client/global/documents/products/data-sheet/nor-flash/serial- > >> nor/mt25t/generation- > >> > b/mt25t_qljs_l_512_xba_0.pdf?rev=de70b770c5dc4da8b8ead06b57c03500 > >> > >> The micron's "Separate Chip-Select and Clock Signals" resembles the > >> AMD's dual parallel 8-bit. > > Yes, I agree. > > > >> Micron's "Shared Chip-Select and Clock Signals" differs from the > >> AMD's stacked mode, as Micron uses DQ[3:0] and DQ[7:4], whereas AMD > >> considers both as DQ[3:0]. > > Yes, correct. > > Amit, please help me to assess this. I assume Micron and Microchip is using > the same concepts as AMD uses for the "Dual Parallel 8-bit IO mode", but > they call it "Twin Quad Mode". That's accurate. It's the same concept. > > I was wrong, the AMD datasheet [1] was misleading [2], it described the IOs > for both flashes as IO[3:0], but later on in the "Table QSPI Interface Signals" > the second flash is described with IO[7:4]. That’s correct. > > The AMD's 8-bit Dual Flash Parallel Interface is using dedicated CS# and CLK# > lines for each flash. As Micron does, isn't it? Correct. > > Micron says [3] that: > "The device contains two quad I/O die, each able to operate independently > for a total of eight I/Os. The memory map applies to each die. Each die has > internal registers for status, configuration, and device protection that can be > set and read independently from one other. > Micron recommends that internal configuration settings for the two die be set > identically." > > it also says that: > "When using quad commands in XIO-SPI or when using QIO-SPI, > DQ[3:0]/DQ[7:4] are I/O." > > So I guess the upper layers just ask for a chunk of memory to be written and > the controller handles the cs# lines automatically. How is the AMD controller > working, do you have to drive the cs# lines manually, or you just set the > parallel mode and the controller takes care of everything? https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Word-Format In parallel mode, the driver sets both the CS_LOWER and CS_UPPER bits in the Cmd_FIFO_Data register(please refer the above link), and sets BUS_SEL to 2’b11 to utilize all 8 IO lines. The controller then manages the assertion and de-assertion of the CS# lines. > > I assume this is how mchp is handling things, they seem to just set a bit the > protocol into the QSPI_IFR.PROTTYP register field and that's all [4]. They even > seem to write the registers of both flashes at the same time. Yes, that's accurate, but the key distinction is that in Microchip, the QSPI controller has one CS# (referred to as QCS), whereas the AMD QSPI controller has 2 CS#(referred to as CS0 & CS1). Regards, Amit > > In what regards the AMD's "dual stack interface", AMD is sharing the clock > and IO lines and uses dedicated CS# lines for the flashes, whereas Micron > shares the CS# and CLK# lines with different IO lines. > > Amit, please study the architectures used by mchp, micron and amd and let > us know if they are the same or they differ, and if they differ what are the > differences. > > I added Conor from mchp in cc, I see Nicolas is already there, and Bean from > micron. > > Thanks, > ta > > [1] > https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/QSPI-Flash-Interface- > Signals > [2] > https://docs.xilinx.com/viewer/attachment/dwmjhDJGICdJqD4swyVzcQ/fD8nv > 4ry78xM0_EF5kv4mA > [3] > https://media-www.micron.com/- > /media/client/global/documents/products/data-sheet/nor-flash/serial- > nor/mt25t/generation- > b/mt25t_qljs_l_512_xba_0.pdf?rev=de70b770c5dc4da8b8ead06b57c03500 > [4] > https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ > ProductDocuments/DataSheets/SAMA7G5-Series-Data-Sheet- > DS60001765.pdf
