On 27 November 2019 16:41, Mark Brown wrote: > > The PLL in the codec relies on MCLK. The MCLK rate can be specified/configured > > by a machine driver using the relevant codec sysclk function, as is done in a > > number of drivers. Surely that has to happen first before we configure the PLL > > as the PLL functions needs to know what rate is coming in so the correct > > dividers can be applied for the required internal clocking to match up with the > > desired sample rates. I guess I'm still missing something regarding your > > discussion around SYSCLK? > > The PLL configuration specifies both input and output clock rates (as > well as an input clock source) so if it's got to configure the MCLK I'd > expect the driver to figure that out without needing the caller to > separately set the MCLK rate. Yes it does but the name of the function implies it's setting the codec's PLL, not the system clock, whereas the other function implies setting the system clock and not the PLL. Also generally you're only setting the sysclk once whereas you may want to configure and enable/disable the PLL more dynamically, at least for devices which do have a built-in PLL. Of course that could still be handled through the single PLL function call. Just as an informational, what's the future for these two functions if essentially one is only really required and the other deemed redundant? I would just like to be clear so I'm not falling over things like this in the future, and wasting your time as well. Seems that the PLL call isn't part of simple generic card code so would the be deemed surplus to requirements some point down the line? _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx https://mailman.alsa-project.org/mailman/listinfo/alsa-devel
