On Wed, Nov 27, 2019 at 04:33:12PM +0000, Adam Thomson wrote: > On 27 November 2019 15:41, Mark Brown wrote: > > Not sure I follow here - if we're configuring the PLL explicitly then > > I'd expect the PLL to be configured first, then the SYSCLK, so I'd > > expect that the automatic PLL configuration wouldn't kick in. > The PLL in the codec relies on MCLK. The MCLK rate can be specified/configured > by a machine driver using the relevant codec sysclk function, as is done in a > number of drivers. Surely that has to happen first before we configure the PLL > as the PLL functions needs to know what rate is coming in so the correct > dividers can be applied for the required internal clocking to match up with the > desired sample rates. I guess I'm still missing something regarding your > discussion around SYSCLK? The PLL configuration specifies both input and output clock rates (as well as an input clock source) so if it's got to configure the MCLK I'd expect the driver to figure that out without needing the caller to separately set the MCLK rate.
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