On 27 November 2019 15:41, Mark Brown wrote: > On Wed, Nov 27, 2019 at 01:42:54PM +0000, Adam Thomson wrote: > > > nicest solution here though. I guess we're stuck with people having to manually > > configure the PLL for bypass when a non-generic machine driver inits, to avoid > > the initial double config, as I don't see other options unless you have > > something to specify at init that it's auto or manual, and this doesn't feel > > like a DT device specific property thing as it's more software than hardware. > > At least Sebastian's patch has a good comment block to highlight this. > > Not sure I follow here - if we're configuring the PLL explicitly then > I'd expect the PLL to be configured first, then the SYSCLK, so I'd > expect that the automatic PLL configuration wouldn't kick in. The PLL in the codec relies on MCLK. The MCLK rate can be specified/configured by a machine driver using the relevant codec sysclk function, as is done in a number of drivers. Surely that has to happen first before we configure the PLL as the PLL functions needs to know what rate is coming in so the correct dividers can be applied for the required internal clocking to match up with the desired sample rates. I guess I'm still missing something regarding your discussion around SYSCLK? _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx https://mailman.alsa-project.org/mailman/listinfo/alsa-devel
