Re: no sound with SondBlast PCI (ens1371)

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Rene Herman <rene.herman <at> keyaccess.nl> writes:

>
> On 20-07-08 02:56, Media Fan wrote:
>
> > Just so so at them, but now I have to put this issue aside due to
> > limited bandwidth. Sorry about this.
>
> <shrug>
>
> Attached you'll find a patch that (with a wide brush) adds delays after
> any and all AC97 related accesses. Was generated against 2.6.26 and
> should apply against 2.6.25(.x) as well.
>
> If you know what to do with it and can, great, if not, never mind. It
> has some potential but is definitely not guaranteed to fix anything. If
> it would be, we'd be removing delays again until we'd find the needed one.
>
> I do wonder a bit about the usefulness of an alsa-user list if most
> problems that wind up here (generally after having gone through some
> crummy web-forum first) are fundamental enough to need patches and
> testing yet the users cannot be expected to be able to.
>
> Ah, I know... let's keep alsa-user and close all crummy web-fora instead!
>
> Rene.
>
>
> diff --git a/sound/pci/ens1370.c b/sound/pci/ens1370.c
> index fbf1124..33e3fcf 100644
> --- a/sound/pci/ens1370.c
> +++ b/sound/pci/ens1370.c
> @@ -518,6 +518,7 @@ static unsigned int snd_es1371_wait_src_ready(struct
ensoniq * ensoniq)
>
>   for (t = 0; t < POLL_COUNT; t++) {
>       r = inl(ES_REG(ensoniq, 1371_SMPRATE));
> +     udelay(100);
>       if ((r & ES_1371_SRC_RAM_BUSY) == 0)
>           return r;
>       cond_resched();
> @@ -539,6 +540,7 @@ static unsigned int snd_es1371_src_read(struct ensoniq *
ensoniq, unsigned short
>           ES_1371_DIS_P2 | ES_1371_DIS_R1);
>   r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
>   outl(r, ES_REG(ensoniq, 1371_SMPRATE));
> + udelay(100);
>
>   /* now, wait for busy and the correct time to read */
>   temp = snd_es1371_wait_src_ready(ensoniq);
> @@ -547,6 +549,7 @@ static unsigned int snd_es1371_src_read(struct ensoniq *
ensoniq, unsigned short
>       /* wait for the right state */
>       for (i = 0; i < POLL_COUNT; i++) {
>           temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
> +         udelay(100);
>           if ((temp & 0x00870000) == 0x00010000)
>               break;
>       }
> @@ -557,6 +560,7 @@ static unsigned int snd_es1371_src_read(struct ensoniq *
ensoniq, unsigned short
>          ES_1371_DIS_P2 | ES_1371_DIS_R1);
>   r |= ES_1371_SRC_RAM_ADDRO(reg);
>   outl(r, ES_REG(ensoniq, 1371_SMPRATE));
> + udelay(100);
>
>   return temp;
>  }
> @@ -571,6 +575,7 @@ static void snd_es1371_src_write(struct ensoniq *ensoniq,
>        ES_1371_DIS_P2 | ES_1371_DIS_R1);
>   r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
>   outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
> + udelay(100);
>  }
>
>  #endif /* CHIP1371 */
> @@ -611,11 +616,13 @@ static void snd_es1371_codec_write(struct snd_ac97
*ac97,
>   mutex_lock(&ensoniq->src_mutex);
>   for (t = 0; t < POLL_COUNT; t++) {
>       if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
> +         udelay(100);
>           /* save the current state for latter */
>           x = snd_es1371_wait_src_ready(ensoniq);
>           outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
>                      ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
0x00010000,
>                ES_REG(ensoniq, 1371_SMPRATE));
> +         udelay(100);
>           /* wait for not busy (state 0) first to avoid
>              transition states */
>           for (t = 0; t < POLL_COUNT; t++) {
> @@ -623,16 +630,20 @@ static void snd_es1371_codec_write(struct snd_ac97
*ac97,
>                   0x00000000)
>                   break;
>           }
> +         udelay(100);
>           /* wait for a SAFE time to write addr/data and then do
it, dammit */
>           for (t = 0; t < POLL_COUNT; t++) {
>               if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) &
0x00870000) ==
>                   0x00010000)
>                   break;
>           }
> +         udelay(100);
>           outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq,
1371_CODEC));
> +         udelay(100);
>           /* restore SRC reg */
>           snd_es1371_wait_src_ready(ensoniq);
>           outl(x, ES_REG(ensoniq, 1371_SMPRATE));
> +         udelay(100);
>           mutex_unlock(&ensoniq->src_mutex);
>           return;
>       }
> @@ -652,11 +663,13 @@ static unsigned short snd_es1371_codec_read(struct
snd_ac97 *ac97,
>   mutex_lock(&ensoniq->src_mutex);
>   for (t = 0; t < POLL_COUNT; t++) {
>       if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
> +         udelay(100);
>           /* save the current state for latter */
>           x = snd_es1371_wait_src_ready(ensoniq);
>           outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
>                      ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
0x00010000,
>                ES_REG(ensoniq, 1371_SMPRATE));
> +         udelay(100);
>           /* wait for not busy (state 0) first to avoid
>              transition states */
>           for (t = 0; t < POLL_COUNT; t++) {
> @@ -664,24 +677,30 @@ static unsigned short snd_es1371_codec_read(struct
snd_ac97 *ac97,
>                   0x00000000)
>                   break;
>           }
> +         udelay(100);
>           /* wait for a SAFE time to write addr/data and then do
it, dammit */
>           for (t = 0; t < POLL_COUNT; t++) {
>               if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) &
0x00870000) ==
>                   0x00010000)
>                   break;
>           }
> +         udelay(100);
>           outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq,
1371_CODEC));
> +         udelay(100);
>           /* restore SRC reg */
>           snd_es1371_wait_src_ready(ensoniq);
>           outl(x, ES_REG(ensoniq, 1371_SMPRATE));
> +         udelay(100);
>           /* wait for WIP again */
>           for (t = 0; t < POLL_COUNT; t++) {
>               if (!(inl(ES_REG(ensoniq, 1371_CODEC)) &
ES_1371_CODEC_WIP))
>                   break;
>           }
> +         udelay(100);
>           /* now wait for the stinkin' data (RDY) */
>           for (t = 0; t < POLL_COUNT; t++) {
>               if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) &
ES_1371_CODEC_RDY) {
> +                 udelay(100);
>                   mutex_unlock(&ensoniq->src_mutex);
>                   return ES_1371_CODEC_READ(x);
>               }
>
>
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I've been having the exact same issues.  I had an on-board hda-intel card that
mysteriously quit working during some upgrade, so i disabled it and bought a
PCI card that ended up being a Creative Vibra128 (EV1938 chip)

I've applied the patch you listed and upon issuing a modprobe snd-ens1371 i
get the following:

ACPI: PCI Interrupt 0000:01:09.0[A] -> Link [APC2] -> GSI 17 (level, low)
    -> IRQ 17
ALSA /home/rand/alsa/1.0.17/alsa-driver-1.0.17/pci/ens1370.c:713: codec read
    timeout (final) at 0xcc14, reg = 0x7c [0x7c8384]
ALSA /home/rand/alsa/1.0.17/alsa-driver-1.0.17/pci/ens1370.c:713: codec read
    timeout (final) at 0xcc14, reg = 0x7e [0x7e7605]
ALSA /home/rand/alsa/1.0.17/alsa-driver-1.0.17/pci/ens1370.c:713: codec read
    timeout (final) at 0xcc14, reg = 0x0 [0x40000140]
ALSA /home/rand/alsa/1.0.17/alsa-driver-1.0.17/pci/ens1370.c:713: codec read
    timeout (final) at 0xcc14, reg = 0x7c [0x7c8384]
ALSA /home/rand/alsa/1.0.17/alsa-driver-1.0.17/pci/ens1370.c:713: codec read
    timeout (final) at 0xcc14, reg = 0x7e [0x7e7605]
ALSA /home/rand/alsa/1.0.17/alsa-driver-1.0.17/pci/ens1370.c:713: codec read
    timeout (final) at 0xcc14, reg = 0x7c [0x7c8384]
ALSA /home/rand/alsa/1.0.17/alsa-driver-1.0.17/pci/ens1370.c:713: codec read
    timeout (final) at 0xcc14, reg = 0x7e [0x7e7605]
ALSA /home/rand/alsa/1.0.17/alsa-driver-1.0.17/pci/ac97/ac97_codec.c:2071:
    AC'97 0 access is not valid [0x0], removing mixer.
ACPI: PCI interrupt for device 0000:01:09.0 disabled
ENS1371: probe of 0000:01:09.0 failed with error -5

uname -a:
Linux saidin 2.6.24-19-generic #1 SMP Fri Jul 11 21:01:46 UTC 2008 x86_64
    GNU/Linux

latest ALSA download, 1.0.17

Relevant lspci -vv section:
01:09.0 Multimedia audio controller: Creative Labs Ectiva EV1938
        Subsystem: Creative Labs Unknown device 5938
        Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
            Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort+
            <MAbort- >SERR- <PERR-
        Interrupt: pin A routed to IRQ 17
        Region 0: I/O ports at cc00 [size=64]
        Region 1: I/O ports at c800 [size=32]
        Capabilities: [dc] Power Management version 2
                Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA
                    PME(D0+,D1+,D2+,D3hot+,D3cold-)
                Status: D3 PME-Enable- DSel=0 DScale=0 PME-


I will be able to run any further tests you may have for me...just let me know!

Jason



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