On Mon, 22 Jan 2024 15:13:31 +0100, Ahmad Fatoum wrote:
> ddrphy_init_set_dfi_clk() is called to translate a scalar clock rate
> as specified by board code into PLL parameters, which are configured.
>
> enum ddr_rate describes the possible DDR rates and so far
> ddrphy_init_set_dfi_clk() supported all of them, except for 2600 and
> 2376 MHz, rendering these two rates unusable.
>
> [...]
Applied, thanks!
[1/1] ddr: imx8m: add missing DDR clock rates
https://git.pengutronix.de/cgit/barebox/commit/?id=205a77e12cd1 (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
